- 专利标题： Reducing capacitive loading of memory system based on switches
-
申请号： US17460216申请日： 2021-08-28
-
公开(公告)号： US11823769B2公开(公告)日： 2023-11-21
- 发明人: Meng-Sheng Chang , Chia-En Huang , Yi-Ching Liu , Yih Wang
- 申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
- 申请人地址： TW Hsinchu
- 专利权人： Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人： Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人地址： TW Hsinchu
- 代理机构： FOLEY & LARDNER LLP
- 主分类号： G11C7/12
- IPC分类号： G11C7/12 ; G11C5/14 ; G11C5/02 ; H01L27/06
摘要：
Disclosed herein are related to a memory array. In one aspect, the memory array includes a first set of memory cells including a first subset of memory cells and a second subset of memory cells. In one aspect, the memory array includes a first switch including a first electrode connected to first electrodes of the first subset of memory cells, and a second electrode connected to a first global line. In one aspect, the memory array includes a second switch including a first electrode connected to first electrodes of the second subset of memory cells, and a second electrode connected to the first global line.
公开/授权文献
信息查询
