- 专利标题: Low latency, broadband power-domain offset-correction signal level circuit implementation
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申请号: US17712026申请日: 2022-04-01
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公开(公告)号: US11824530B2公开(公告)日: 2023-11-21
- 发明人: Mohammad Radfar , Ichiro Aoki , Scott David Kee
- 申请人: AyDeeKay LLC
- 申请人地址: US CA Aliso Viejo
- 专利权人: AyDeeKay LLC
- 当前专利权人: AyDeeKay LLC
- 当前专利权人地址: US CA Aliso Viejo
- 代理商 Steven Stupp
- 主分类号: H03K19/00
- IPC分类号: H03K19/00 ; H03K19/0175 ; H03K5/1252 ; H03K19/0185
摘要:
An interface circuit may convert an input electrical signal at an input node in a first power domain having a first ground or reference voltage into an output electrical signal at an output node in a second power domain having a second ground or reference voltage. Notably, a level-shifting circuit in the interface circuit may selectively electrically couple to the input node and the output node. Then, when there is electrical coupling, the level-shifting circuit may perform level shifting between the first power domain and the second power domain. The level shifting may involve: passing, using a first filter, frequencies in the input electrical signal below a first corner frequency; passing, using a second filter in parallel with the first filter, frequencies in the input electrical signal above a second corner frequency; and combining outputs of the first filter and the second filter as the output electrical signal.
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