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公开(公告)号：US11914022B2
公开(公告)日：2024-02-27
申请号：US18132409
申请日：2023-04-09
申请人： AyDeeKay LLC
发明人： Tom Heller
IPC分类号： G01S13/58 , G01S13/34 , G01S13/534
CPC分类号： G01S13/584 , G01S13/343 , G01S13/534
摘要： In an illustrative integrated circuit, a chirp generator provides a chirp signal having linearly-ramped chirp intervals, while a shift frequency generator provides a signal having a different shift frequency during each of multiple segments in each chirp interval. A modulator combines the signals to derive a segmented chirp signal having multiple linearly-ramped chirp segments in each chirp interval. The modulator may be a single sideband modulator to provide frequency up-shifted and frequency down-shifted chirp segments. The segmented chirp signal may be suppressed during resettling intervals of the original chirp signal.
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公开(公告)号：US20230318788A1
公开(公告)日：2023-10-05
申请号：US18126856
申请日：2023-03-27
发明人： Rakhel Parida
CPC分类号： H04L5/0053 , H04W56/0015
摘要： An integrated circuit with an interface circuit is described. During operation, the interface circuit may receive signals corresponding to a header of a frame that is compatible with a serial communication protocol, where the received signals include a temporal pattern of binary bits with instances of a dominant signal level and a recessive signal level. Then, the interface circuit may compute a set of conditions based at least in part on the receive signals, where, when valid, the set of conditions identify a first dominant bit in the binary bits having the dominant signal level. Moreover, when the set of conditions are valid, the interface circuit may: determine a location of synchronization field in the header relative to the identified first dominant bit; and calculate a baud rate of the receive signals based at least in part on a subset of the binary bits in the synchronization field.
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公开(公告)号：US11726935B2
公开(公告)日：2023-08-15
申请号：US17315271
申请日：2021-05-08
申请人： AyDeeKay LLC
发明人： Scott David Kee
IPC分类号： G06F3/00 , G06F13/26 , G06F13/40 , G06F3/06 , G06F12/06 , G06F12/0866 , G06F13/16 , G06F13/28 , G06F13/364 , G06F13/42 , G06F13/14 , G06F21/76
CPC分类号： G06F13/26 , G06F3/0659 , G06F3/0679 , G06F12/0638 , G06F12/0866 , G06F13/14 , G06F13/1668 , G06F13/1684 , G06F13/28 , G06F13/364 , G06F13/4027 , G06F13/4068 , G06F13/4282 , G06F21/76 , G06F2213/0062 , G06F2213/40 , G06F2221/2103
摘要： Techniques in electronic systems, such as in systems comprising a CPU die and one or more external mixed-mode (analog) chips, may provide improvements advantages in one or more of system design, performance, cost, efficiency and programmability. In one embodiment, the CPU die comprises at least one microcontroller CPU and circuitry enabling the at least one CPU to have a full and transparent connectivity to an analog chip as if they are designed as a single chip microcontroller, while the interface design between the two is extremely efficient and with limited in number of wires, yet may provide improved performance without impact to functionality or the software model.
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4.发明申请公开(公告)号：US20220149858A1
公开(公告)日：2022-05-12
申请号：US17322869
申请日：2021-05-17
IPC分类号： H03M1/10
摘要： An analog-to-digital converter (ADC) is described. This ADC includes a conversion circuit with multiple bit-conversion circuits. During operation, the ADC may receive an input signal. Then, the conversion circuit may asynchronously perform successive-approximation-register (SAR) analog-to-digital conversion of the input signal using the bit-conversion circuits, where the bit-conversion circuits to provide a quantized representation of the input signal. For example, the bit-conversion circuits may asynchronously and sequentially perform the SAR analog-to-digital conversion to determine different bits in the quantized representation of the input signal. Moreover, the ADC may selectively perform self-calibration of a global delay of the bit-conversions circuits. Note that the timing self-calibration may be iterative and subject to a constraint that a maximum conversion time is less than a target conversion time.
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公开(公告)号：US20220038112A1
公开(公告)日：2022-02-03
申请号：US17322862
申请日：2021-05-17
发明人： Scott David Kee , Setu Mohta
IPC分类号： H03M1/12
摘要： Analog-to-digital converters (ADCs) with a high sampling rate and larger spurious-free dynamic range (SFDR) in the spectral domain are used in many applications, including, but not limited to, range finders, meteorology, spectroscopy, and/or coherent medical imaging. Circuit techniques for time-interleaving a set of low-sampling-rate sub-ADCs into a higher sampling-rate ADC with a larger SFDR than existing approaches are described. In one embodiment, the circuit techniques add a small number of additional units or sub-ADCs. This change in architecture enables a dynamic-selection procedure to time-interleave the set of sub-ADCs in such a way that mismatch-related non-idealities of the constituent sub-ADCs are spread in the frequency domain into a noise-like spectral shape in order to prevent the creation of spurious tones, which would otherwise deleteriously impact the SFDR.
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公开(公告)号：US11239845B1
公开(公告)日：2022-02-01
申请号：US17322880
申请日：2021-05-17
申请人： AyDeeKay LLC
发明人： Jim Wilshire
IPC分类号： H03L7/08
摘要： An integrated circuit is described. This integrated circuit may include an input connector, coupled to a signal line, that conveys an input signal corresponding to encoded data, where the encoded data is encoded using a BMC, and the input signal may have different rise times and fall times. Moreover, the integrated circuit may include a recovery circuit, coupled to the input connector, that outputs the data based at least in part on a first threshold and a second threshold, where the output data may include data values with equal half-bit periods and variable frequency. Note that the recovery circuit may implement a state machine corresponding to the data.
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公开(公告)号：US20210326489A1
公开(公告)日：2021-10-21
申请号：US17315271
申请日：2021-05-08
发明人： Scott David Kee
IPC分类号： G06F21/76
摘要： Techniques in electronic systems, such as in systems comprising a CPU die and one or more external mixed-mode (analog) chips, may provide improvements advantages in one or more of system design, performance, cost, efficiency and programmability. In one embodiment, the CPU die comprises at least one microcontroller CPU and circuitry enabling the at least one CPU to have a full and transparent connectivity to an analog chip as if they are designed as a single chip microcontroller, while the interface design between the two is extremely efficient and with limited in number of wires, yet may provide improved performance without impact to functionality or the software model.
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公开(公告)号：US20210326073A1
公开(公告)日：2021-10-21
申请号：US17315267
申请日：2021-05-08
发明人： Scott David Kee
IPC分类号： G06F3/06 , G06F12/06 , G06F12/0866
摘要： A system that includes a first die with a central processing unit (CPU) and a second die electrically coupled to the first die by die-to-die interconnects is described. During operation, the first die: provides, to the second die, a set of predefined wake-up events; provides, to the second die, a message that transitions power-management control of the first die to the second die; and transitions the first die from a first operating mode to a second operating mode that has lower power consumption than that of the first operating mode. Then, the second die: determines an occurrence of a predefined wake-up event based at least in part on the set of predefined wake-up events; and provides, to the first die, information that initiates a transition of the first die from the second operating mode to the first operating mode.
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公开(公告)号：US20240340019A1
公开(公告)日：2024-10-10
申请号：US18745800
申请日：2024-06-17
摘要： A conversion circuit that performs analog-to-digital conversion is described. During operation, the conversion circuit receives an input signal. Then, the conversion circuit performs analog-to-digital conversion and provides a quantized output corresponding to the input signal based at least in part on a first power-supply voltage and a second power-supply voltage of the conversion circuit. For example, the quantized output may be based at least in part on a comparison of the input signal to the first power-supply voltage and the second power-supply voltage. Moreover, the first power-supply voltage and the second power-supply voltage may specify a full-scale range of the conversion circuit. When the full-scale range exceeds a second full-scale range associated with reference voltages that are other than the first power-supply voltage and the second power-supply voltage, the quantized output may correspond to a larger number of bits than when the full-scale range equals the second full-scale range.
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10.发明公开公开(公告)号：US20240235550A9
公开(公告)日：2024-07-11
申请号：US18383477
申请日：2023-10-25
发明人： Mohammad Radfar , Ichiro Aoki , Scott David Kee
IPC分类号： H03K19/0175 , H03K5/1252 , H03K19/0185
CPC分类号： H03K19/017509 , H03K5/1252 , H03K19/0185 , H03K19/018514
摘要： An interface circuit may convert an input electrical signal at an input node in a first power domain having a first ground or reference voltage into an output electrical signal at an output node in a second power domain having a second ground or reference voltage. Notably, a level-shifting circuit in the interface circuit may selectively electrically couple to the input node and the output node. Then, when there is electrical coupling, the level-shifting circuit may perform level shifting between the first power domain and the second power domain. The level shifting may involve: passing, using a first filter, frequencies in the input electrical signal below a first corner frequency; passing, using a second filter in parallel with the first filter, frequencies in the input electrical signal above a second corner frequency; and combining outputs of the first filter and the second filter as the output electrical signal.
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