- Patent Title: Integrated circuit device die with wafer/package detection circuit
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Application No.: US16527296Application Date: 2019-07-31
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Publication No.: US11842934B2Publication Date: 2023-12-12
- Inventor: Jan-Peter Schat
- Applicant: NXP B.V.
- Applicant Address: NL Eindhoven
- Assignee: NXP B.V.
- Current Assignee: NXP B.V.
- Current Assignee Address: NL Eindhoven
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L21/66 ; G06F21/76 ; G01R31/28

Abstract:
A mechanism is provided to secure integrated circuit devices that combines a high degree of security with a low overhead, both in area and cost, thereby making it appropriate for smaller, cheaper integrated circuits. A determination is made whether a device die is on a wafer or if the device die is incorporated into a package. Only if the device die is incorporated in a package can the functional logic of device die be activated, and then only if a challenge-response query is satisfied. In some embodiments, a random number generator is used during wafer testing to form a pair of numbers, along with a die identifier, that is unique for each device die. A final test is then performed in which the device die can be activated if the device die is incorporated in a package, and the die identifier—random number pair is authenticated.
Public/Granted literature
- US20210035923A1 Preventing and Detecting Integrated Circuit Theft and Counterfeiting Public/Granted day:2021-02-04
Information query
IPC分类: