Invention Grant
- Patent Title: Die stack with reduced warpage
-
Application No.: US17391612Application Date: 2021-08-02
-
Publication No.: US11848281B2Publication Date: 2023-12-19
- Inventor: Yong She , Bin Liu , Zhicheng Ding , Aiping Tan
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Akona IP
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L25/065 ; H01L23/498 ; G11C5/04 ; H10B41/35 ; H10B43/35

Abstract:
A microelectronic device can include a polymer, a semiconductor, and a matching layer. The polymer can include a first coefficient of thermal expansion. The semiconductor can be coupled to the polymer layer. The matching layer can be adjacent the semiconductor, and the matching layer can include a second coefficient of thermal expansion that is about the same as the first coefficient of thermal expansion.
Public/Granted literature
- US20220020704A1 DIE STACK WITH REDUCED WARPAGE Public/Granted day:2022-01-20
Information query
IPC分类: