Invention Grant
- Patent Title: Generating integrated circuit placements using neural networks
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Application No.: US18082392Application Date: 2022-12-15
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Publication No.: US11853677B2Publication Date: 2023-12-26
- Inventor: Anna Darling Goldie , Azalia Mirhoseini , Ebrahim Songhori , Wenjie Jiang , Shen Wang , Roger David Carpenter , Young-Joon Lee , Mustafa Nazim Yazgan , Chian-min Richard Ho , Quoc V. Le , James Laudon , Jeffrey Adgate Dean , Kavya Srinivasa Setty , Omkar Pathak
- Applicant: Google LLC
- Applicant Address: US CA Mountain View
- Assignee: Google LLC
- Current Assignee: Google LLC
- Current Assignee Address: US CA Mountain View
- Agency: Fish & Richardson P.C.
- The original application number of the division: US17238128 2021.04.22
- Main IPC: G06F30/392
- IPC: G06F30/392 ; G06F30/398 ; G06N3/08

Abstract:
Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a computer chip placement. One of the methods includes obtaining netlist data for a computer chip; and generating a computer chip placement, comprising placing a respective macro node at each time step in a sequence comprising a plurality of time steps, the placing comprising, for each time step: generating an input representation for the time step; processing the input representation using a node placement neural network having a plurality of network parameters, wherein the node placement neural network is configured to process the input representation in accordance with current values of the network parameters to generate a score distribution over a plurality of positions on the surface of the computer chip; and assigning the macro node to be placed at the time step to a position from the plurality of positions using the score distribution.
Public/Granted literature
- US20230117786A1 GENERATING INTEGRATED CIRCUIT PLACEMENTS USING NEURAL NETWORKS Public/Granted day:2023-04-20
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