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    Generating integrated circuit floorplans using neural networks
    2.
    发明授权
    Generating integrated circuit floorplans using neural networks 有权

    公开(公告)号：US11675940B2

    公开(公告)日：2023-06-13

    申请号：US17409566

    申请日：2021-08-23

    Applicant: Google LLC

    Inventor： Chian-Min Richard Ho ,  William Hang ,  Mustafa Nazim Yazgan ,  Anna Darling Goldie ,  Jeffrey Adgate Dean ,  Azalia Mirhoseini ,  Emre Tuncer ,  Ya Wang ,  Anand Babu

    IPC: G06F30/27 ,  G06F30/392

    CPC classification number: G06F30/27 ,  G06F30/392

    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a computer chip floorplan. One of the methods includes obtaining netlist data for a computer chip; and generating a computer chip floorplan, comprising placing a respective node at each time step in a sequence comprising a plurality of time steps, the placing comprising, for each time step: generating an input representation for the time step; processing the input representation using a node placement neural network having a plurality of network parameters, wherein the node placement neural network is configured to process the input representation in accordance with current values of the network parameters to generate a score distribution over a plurality of positions on the surface of the computer chip; and assigning the node to be placed at the time step to a position from the plurality of positions using the score distribution.

    Hierarchical device placement with reinforcement learning
    3.
    发明授权
    Hierarchical device placement with reinforcement learning 有权

    公开(公告)号：US10438113B2

    公开(公告)日：2019-10-08

    申请号：US16040186

    申请日：2018-07-19

    Applicant: Google LLC

    Inventor： Benoit Steiner ,  Anna Darling Goldie ,  Jeffrey Adgate Dean ,  Hieu Hy Pham ,  Azalia Mirhoseini ,  Quoc V. Le

    IPC: G06N3/04 ,  G06N20/00 ,  G06F16/901 ,  G06N3/063 ,  G06N3/08 ,  G06N5/04 ,  G06F9/50

    Abstract: A method for determining a placement for machine learning model operations across multiple hardware devices includes receiving data specifying machine learning operations, and determining a placement that assigns each of the operations specified by the data to a respective device from the multiple hardware devices. Determining the placement includes: generating, from the data, a respective operation embedding for each of the operations; grouping the operations into multiple operation groups, comprising processing each of the respective operation embeddings using a grouper neural network having multiple grouper parameters, in which the grouper neural network is configured to, for each of the operations, process the operation embedding for the operation in accordance with first values of the grouper parameters to generate a grouper output that assigns the operation to an operation group from the multiple operation groups; and assigning each of the operation groups to a respective device from the multiple hardware devices.

    GENERATING INTEGRATED CIRCUIT FLOORPLANS USING NEURAL NETWORKS
    6.
    发明公开
    GENERATING INTEGRATED CIRCUIT FLOORPLANS USING NEURAL NETWORKS 审中-公开

    公开(公告)号：US20230394203A1

    公开(公告)日：2023-12-07

    申请号：US18310427

    申请日：2023-05-01

    Applicant: Google LLC

    Inventor： Chian-min Richard Ho ,  William Hang ,  Mustafa Nazim Yazgan ,  Anna Darling Goldie ,  Jeffrey Adgate Dean ,  Azalia Mirhoseini ,  Emre Tuncer ,  Ya Wang ,  Anand Babu

    IPC: G06F30/27 ,  G06F30/392

    CPC classification number: G06F30/27 ,  G06F30/392

    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a computer chip floorplan. One of the methods includes obtaining netlist data for a computer chip; and generating a computer chip floorplan, comprising placing a respective node at each time step in a sequence comprising a plurality of time steps, the placing comprising, for each time step: generating an input representation for the time step; processing the input representation using a node placement neural network having a plurality of network parameters, wherein the node placement neural network is configured to process the input representation in accordance with current values of the network parameters to generate a score distribution over a plurality of positions on the surface of the computer chip; and assigning the node to be placed at the time step to a position from the plurality of positions using the score distribution.

    Generating integrated circuit floorplans using neural networks
    7.
    发明授权
    Generating integrated circuit floorplans using neural networks 有权

    公开(公告)号：US11100266B2

    公开(公告)日：2021-08-24

    申请号：US16889130

    申请日：2020-06-01

    Applicant: Google LLC

    Inventor： Chian-min Richard Ho ,  William Hang ,  Mustafa Nazim Yazgan ,  Anna Darling Goldie ,  Jeffrey Adgate Dean ,  Azalia Mirhoseini ,  Emre Tuncer ,  Ya Wang ,  Anand Babu

    IPC: G06F30/00 ,  G06F30/30 ,  G06F30/27 ,  G06F30/392

    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a computer chip floorplan. One of the methods includes obtaining netlist data for a computer chip; and generating a computer chip floorplan, comprising placing a respective node at each time step in a sequence comprising a plurality of time steps, the placing comprising, for each time step: generating an input representation for the time step; processing the input representation using a node placement neural network having a plurality of network parameters, wherein the node placement neural network is configured to process the input representation in accordance with current values of the network parameters to generate a score distribution over a plurality of positions on the surface of the computer chip; and assigning the node to be placed at the time step to a position from the plurality of positions using the score distribution.

    Generating integrated circuit floorplans using neural networks
    9.
    发明授权
    Generating integrated circuit floorplans using neural networks 有权

    公开(公告)号：US12086516B2

    公开(公告)日：2024-09-10

    申请号：US18310427

    申请日：2023-05-01

    Applicant: Google LLC

    Inventor： Chian-min Richard Ho ,  William Hang ,  Mustafa Nazim Yazgan ,  Anna Darling Goldie ,  Jeffrey Adgate Dean ,  Azalia Mirhoseini ,  Emre Tuncer ,  Ya Wang ,  Anand Babu

    IPC: G06F30/27 ,  G06F30/392

    CPC classification number: G06F30/27 ,  G06F30/392

    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a computer chip floorplan. One of the methods includes obtaining netlist data for a computer chip; and generating a computer chip floorplan, comprising placing a respective node at each time step in a sequence comprising a plurality of time steps, the placing comprising, for each time step: generating an input representation for the time step; processing the input representation using a node placement neural network having a plurality of network parameters, wherein the node placement neural network is configured to process the input representation in accordance with current values of the network parameters to generate a score distribution over a plurality of positions on the surface of the computer chip; and assigning the node to be placed at the time step to a position from the plurality of positions using the score distribution.

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