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    GENERATING LEARNED REPRESENTATIONS OF DIGITAL CIRCUIT DESIGNS
    1.
    发明公开
    GENERATING LEARNED REPRESENTATIONS OF DIGITAL CIRCUIT DESIGNS 审中-公开

    公开(公告)号：US20240273270A1

    公开(公告)日：2024-08-15

    申请号：US18564797

    申请日：2022-05-31

    Applicant: Google LLC

    Inventor： Shobha Vasudevan ,  Wenjie Jiang ,  Charles Aloysius Sutton ,  Rishabh Singh ,  David Bieber ,  Milad Olia Hashemi ,  Chian-min Richard Ho ,  Hamid Shojaei

    IPC: G06F30/323 ,  G06F30/33

    CPC classification number: G06F30/323 ,  G06F30/33

    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating learned representations of digital circuit designs. One of the systems includes obtaining data representing a program that implements a digital circuit design, the program comprising a plurality of statements; processing the obtained data to generate data representing a graph representing the digital circuit design, the graph comprising: a plurality of nodes representing respective statements of the program, a plurality of first edges each representing a control flow between a pair of statements of the program, and a plurality of second edges each representing a data flow between a pair of statements of the program; and generating a learned representation of the digital circuit design, comprising processing the data representing the graph using a graph neural network to generate a respective learned representation of each statement represented by a node of the graph.

    GENERATING INTEGRATED CIRCUIT FLOORPLANS USING NEURAL NETWORKS
    5.
    发明公开
    GENERATING INTEGRATED CIRCUIT FLOORPLANS USING NEURAL NETWORKS 审中-公开

    公开(公告)号：US20230394203A1

    公开(公告)日：2023-12-07

    申请号：US18310427

    申请日：2023-05-01

    Applicant: Google LLC

    Inventor： Chian-min Richard Ho ,  William Hang ,  Mustafa Nazim Yazgan ,  Anna Darling Goldie ,  Jeffrey Adgate Dean ,  Azalia Mirhoseini ,  Emre Tuncer ,  Ya Wang ,  Anand Babu

    IPC: G06F30/27 ,  G06F30/392

    CPC classification number: G06F30/27 ,  G06F30/392

    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a computer chip floorplan. One of the methods includes obtaining netlist data for a computer chip; and generating a computer chip floorplan, comprising placing a respective node at each time step in a sequence comprising a plurality of time steps, the placing comprising, for each time step: generating an input representation for the time step; processing the input representation using a node placement neural network having a plurality of network parameters, wherein the node placement neural network is configured to process the input representation in accordance with current values of the network parameters to generate a score distribution over a plurality of positions on the surface of the computer chip; and assigning the node to be placed at the time step to a position from the plurality of positions using the score distribution.

    Generating integrated circuit floorplans using neural networks
    6.
    发明授权
    Generating integrated circuit floorplans using neural networks 有权

    公开(公告)号：US11100266B2

    公开(公告)日：2021-08-24

    申请号：US16889130

    申请日：2020-06-01

    Applicant: Google LLC

    Inventor： Chian-min Richard Ho ,  William Hang ,  Mustafa Nazim Yazgan ,  Anna Darling Goldie ,  Jeffrey Adgate Dean ,  Azalia Mirhoseini ,  Emre Tuncer ,  Ya Wang ,  Anand Babu

    IPC: G06F30/00 ,  G06F30/30 ,  G06F30/27 ,  G06F30/392

    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a computer chip floorplan. One of the methods includes obtaining netlist data for a computer chip; and generating a computer chip floorplan, comprising placing a respective node at each time step in a sequence comprising a plurality of time steps, the placing comprising, for each time step: generating an input representation for the time step; processing the input representation using a node placement neural network having a plurality of network parameters, wherein the node placement neural network is configured to process the input representation in accordance with current values of the network parameters to generate a score distribution over a plurality of positions on the surface of the computer chip; and assigning the node to be placed at the time step to a position from the plurality of positions using the score distribution.

    Generating integrated circuit floorplans using neural networks
    7.
    发明授权
    Generating integrated circuit floorplans using neural networks 有权

    公开(公告)号：US12086516B2

    公开(公告)日：2024-09-10

    申请号：US18310427

    申请日：2023-05-01

    Applicant: Google LLC

    Inventor： Chian-min Richard Ho ,  William Hang ,  Mustafa Nazim Yazgan ,  Anna Darling Goldie ,  Jeffrey Adgate Dean ,  Azalia Mirhoseini ,  Emre Tuncer ,  Ya Wang ,  Anand Babu

    IPC: G06F30/27 ,  G06F30/392

    CPC classification number: G06F30/27 ,  G06F30/392

    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a computer chip floorplan. One of the methods includes obtaining netlist data for a computer chip; and generating a computer chip floorplan, comprising placing a respective node at each time step in a sequence comprising a plurality of time steps, the placing comprising, for each time step: generating an input representation for the time step; processing the input representation using a node placement neural network having a plurality of network parameters, wherein the node placement neural network is configured to process the input representation in accordance with current values of the network parameters to generate a score distribution over a plurality of positions on the surface of the computer chip; and assigning the node to be placed at the time step to a position from the plurality of positions using the score distribution.

    Faster Coverage Convergence with Automatic Test Parameter Tuning in Constrained Random Verification
    8.
    发明公开
    Faster Coverage Convergence with Automatic Test Parameter Tuning in Constrained Random Verification 审中-公开

    公开(公告)号：US20230376645A1

    公开(公告)日：2023-11-23

    申请号：US18248458

    申请日：2021-11-05

    Applicant: Google LLC

    Inventor： Hamid Shojaei ,  Qijing Huang ,  Chian-min Richard Ho ,  Satrajit Chatterjee ,  Shobha Vasudevan ,  Azade Nazi ,  Frederick Dennis Zyda

    IPC: G06F30/17

    CPC classification number: G06F30/17

    Abstract: This document discloses systems and methods for implementing automatic test parameter tuning in constrained random verification. In aspects, a method receives a first set of parameters for testing a design under test, performs a first regression (e.g., an overnight regression test) on a design under test using the first set of parameters, and analyzes the results of the first regression including determining a coverage percentage. The method then generates an optimized set of parameters based on the analysis of the results of the first regression and performs an additional regression on the design under test using the optimized set of parameters. In aspects, the method is repeated using the optimized set of parameters until a coverage percentage is reached, or in some implementations, full coverage may be reached. Some implementations of the method utilize black-box optimization through use of a Bayesian optimization algorithm.

    GENERATING INTEGRATED CIRCUIT FLOORPLANS USING NEURAL NETWORKS
    10.
    发明申请
    GENERATING INTEGRATED CIRCUIT FLOORPLANS USING NEURAL NETWORKS 审中-公开

    公开(公告)号：US20200175216A1

    公开(公告)日：2020-06-04

    申请号：US16703837

    申请日：2019-12-04

    Applicant: Google LLC

    Inventor： Chian-min Richard Ho ,  William Hang ,  Mustafa Nazim Yazgan ,  Anna Darling Goldie ,  Jeffrey Adgate Dean ,  Azalia Mirhoseini ,  Emre Tuncer ,  Ya Wang ,  Anand Babu

    IPC: G06F30/27 ,  G06F30/392

    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a computer chip floorplan. One of the methods includes obtaining netlist data for a computer chip; and generating a computer chip floorplan, comprising placing a respective node at each time step in a sequence comprising a plurality of time steps, the placing comprising, for each time step: generating an input representation for the time step; processing the input representation using a node placement neural network having a plurality of network parameters, wherein the node placement neural network is configured to process the input representation in accordance with current values of the network parameters to generate a score distribution over a plurality of positions on the surface of the computer chip; and assigning the node to be placed at the time step to a position from the plurality of positions using the score distribution.

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