发明授权
- 专利标题： Bi-layer alloy liner for interconnect metallization and methods of forming the same
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申请号： US17066706申请日： 2020-10-09
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公开(公告)号： US11854878B2公开(公告)日： 2023-12-26
- 发明人: Huei-Wen Hsieh , Kai-Shiang Kuo , Cheng-Hui Weng , Chun-Sheng Chen , Wen-Hsuan Chen
- 申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
- 申请人地址： TW Hsinchu
- 专利权人： TAIWAN SEMICONDUCTOR MANUFACTURING LTD.
- 当前专利权人： TAIWAN SEMICONDUCTOR MANUFACTURING LTD.
- 当前专利权人地址： TW Hsinchu
- 代理机构： Slater Matsil, LLP
- 主分类号： H01L25/065
- IPC分类号： H01L25/065 ; H01L25/00 ; H01L21/768 ; H01L23/00 ; H01L23/532 ; H01L23/31 ; H01L23/528 ; H01L23/522 ; H01L27/088
摘要：
A method of forming a semiconductor device includes forming an opening in a dielectric layer, and forming a barrier layer in the opening. A combined liner layer is formed over the barrier layer by first forming a first liner layer over the barrier layer, and forming a second liner layer over the first liner layer, such that the first liner layer and the second liner layer intermix. A conductive material layer is formed over the combined liner layer, and a thermal process is performed to reflow the conductive material layer.
公开/授权文献
- US20210202310A1 BI-LAYER LINER FOR METALLIZATION 公开/授权日：2021-07-01
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