公开(公告)号：US20240304455A1

公开(公告)日：2024-09-12

申请号：US18667585

申请日：2024-05-17

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Ping TSENG ,  Ren-Hao JHENG

IPC分类号： H01L21/321 ,  B24B9/06 ,  B24B37/04 ,  B24B37/24 ,  B24B37/26

CPC分类号： H01L21/3212 ,  B24B9/065 ,  B24B37/044 ,  B24B37/24 ,  B24B37/26

摘要： The present disclosure provides an apparatus and a method for polishing a semiconductor substrate in semiconductor device manufacturing. The apparatus can include: a carrier configured to hold the substrate; a polishing pad configured to polish a first surface of the substrate; a chemical mechanical polishing (CMP) slurry delivery arm configured to dispense a CMP slurry onto the first surface of the substrate; and a pad conditioner configured to condition the polishing pad. In some embodiments, the pad conditioner can include: a conditioning disk configured to scratch the polishing pad; a conditioning arm configured to rotate the conditioning disk; a plurality of magnetic screws configured to secure the conditioning disk onto the conditioning arm and including a respective plurality of screw heads; and a plurality of blocking devices respectively positioned beneath the plurality of screw heads and configured to block debris particles from entering a respective plurality of screw holes.

公开(公告)号：US11831310B2

公开(公告)日：2023-11-28

申请号：US17883257

申请日：2022-08-08

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  TSMC CHINA COMPANY, LIMITED

发明人： Yaqi Ma ,  Lei Pan ,  JunKui Hu

IPC分类号： H03K19/0185 ,  H03K3/037 ,  G06F30/392 ,  H01L27/092 ,  H03K3/356

CPC分类号： H03K19/018521 ,  G06F30/392 ,  H01L27/092 ,  H03K3/037 ,  H03K3/35613 ,  H03K19/0185

摘要： An integrated circuit (IC) includes a first power supply node configured to have a first power supply voltage level, a second power supply node configured to have a second power supply voltage level separate from the first power supply voltage level, an n-well, a bias circuit, and a level shifter. The n-well contains first and second PMOS transistors including first source/drain (S/D) terminals coupled to the first power supply node, and third and fourth PMOS transistors including second S/D terminals coupled to the second power supply node. The bias circuit includes the first PMOS transistor including a third S/D terminal coupled to the n-well and a gate coupled to the second power supply node, and the third PMOS transistor including a fourth S/D terminal coupled to the n-well and a gate coupled to the first power supply node. The level shifter includes the second and fourth PMOS transistors.

公开(公告)号：US6143579A

公开(公告)日：2000-11-07

申请号：US298936

申请日：1999-04-26

申请人： Chia-Der Chang ,  Chi-Hung Liao ,  Dean-E Lin ,  Sheng-Liang Pan

发明人： Chia-Der Chang ,  Chi-Hung Liao ,  Dean-E Lin ,  Sheng-Liang Pan

IPC分类号： H01L21/66 ,  H01L23/544

CPC分类号： H01L22/34 ,  H01L22/12 ,  H01L2924/0002

摘要： It has been observed that, when a commercial plasma etcher is used for multiple etching tasks involving a variety of products, the amount of plasma damage incurred depends upon the chamber history of the etching tool. Thus, etching a gate sidewall spacer on a damage sensitive product, for example, in a MOSFET product with very thin gate oxide, may result in significant degradation of the gate oxide if the plasma etching tool had been used to etch vias on another type product in the preceding job. A method for monitoring and recording the chamber history and ascertaining the status of a plasma etching tool with regard to the tendency of said tool to introduce plasma damage in thin gate and tunnel oxide layers is disclosed. The method includes an a oxide damage monitor wafer which contains arrays of simple test devices. The monitor wafers can be partially formed and banked for later use. The test devices comprise a polysilicon plate partially covering a gate oxide. A conformal oxide is formed over the structure and the wafer is subjected to a spacer etch in the plasma etching tool being appraised. Dielectric breakdown the thin oxide is measured and the data is compared to a chamber history of the etcher. Those etching procedures which adversely affect the chamber are identified. Once a chamber history is established, the etcher can be expeditiously scheduled and the incidence of jobs lost to oxide damage greatly reduced.

摘要翻译： 已经观察到，当商业等离子体蚀刻机用于涉及各种产品的多次蚀刻任务时，所产生的等离子体损伤的量取决于蚀刻工具的腔室历史。 因此，如果已经使用等离子体蚀刻工具蚀刻另一种类型产品上的通孔，则蚀刻损伤敏感产品上的栅极侧壁间隔物（例如，具有非常薄的栅极氧化物的MOSFET产品）可能导致栅极氧化物的显着降解 在前面的工作。 公开了一种用于监测和记录室历史并确定等离子体蚀刻工具关于所述工具在薄栅和隧道氧化物层中引入等离子体损伤的趋势的方法。 该方法包括含有简单测试装置阵列的氧化物损伤监测晶片。 显示器晶片可以部分地形成并分组以供以后使用。 测试装置包括部分覆盖栅极氧化物的多晶硅板。 在结构上形成共形氧化物，并且在评估的等离子体蚀刻工具中对晶片进行间隔蚀刻。 测量介电击穿薄氧化物，并将数据与蚀刻器的室历史进行比较。 识别对腔室有不利影响的蚀刻过程。 一旦建立了房间历史，就可以迅速安排蚀刻器，大大减少对氧化物损失造成的作业的发生。

公开(公告)号：US08927413B2

公开(公告)日：2015-01-06

申请号：US13674887

申请日：2012-11-12

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tsung-Min Huang ,  Chung-Ju Lee

IPC分类号： H01L21/3205 ,  H01L21/768 ,  H01L23/48

CPC分类号： H01L23/5226 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76843 ,  H01L21/76852 ,  H01L21/76865 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/481 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2221/1031 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure and a fabricating process for the same are provided. The semiconductor fabricating process includes providing a first dielectric layer, a transitional layer formed on the first dielectric layer, and a conductive fill penetrated through the transitional layer and into the first dielectric layer; removing the transitional layer; and forming a second dielectric layer over the conductive fill and the first dielectric layer.

摘要翻译： 提供了一种半导体结构及其制造方法。 半导体制造工艺包括提供第一介电层，形成在第一介电层上的过渡层和穿过过渡层并进入第一介电层的导电填料; 去除过渡层; 以及在所述导电填充物和所述第一介电层上形成第二电介质层。

公开(公告)号：US12062540B2

公开(公告)日：2024-08-13

申请号：US17583330

申请日：2022-01-25

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  NATIONAL TAIWAN UNIVERSITY

发明人： Ya-Ting Chang ,  Jian-Zhi Huang ,  Jin-Bin Yang ,  I-Chih Ni ,  Chih-I Wu

IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L21/822 ,  H01L21/84 ,  H01L23/532 ,  H01L27/12 ,  H01L29/66 ,  H01L29/786

CPC分类号： H01L21/02614 ,  H01L21/02568 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/8221 ,  H01L21/84 ,  H01L27/1207 ,  H01L29/66969 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L29/786

摘要： A method for forming an integrated circuit device is provided. The method includes forming a transistor over a frontside of a substrate; forming an interconnect structure over the transistor; depositing a first transition metal layer over the interconnect structure; performing a plasma treatment to turn the first transition metal layer into a first transition metal dichalcogenide layer; forming a dielectric layer over the first transition metal dichalcogenide layer; forming a first gate electrode over the dielectric layer and a first portion of the first transition metal dichalcogenide layer; and forming a first source contact and a first drain contact respectively connected with a second portion and a third portion of the first transition metal dichalcogenide layer, the first portion of the first transition metal dichalcogenide layer being between the second and third portions of the first transition metal dichalcogenide layers.

公开(公告)号：US09117669B2

公开(公告)日：2015-08-25

申请号：US13723001

申请日：2012-12-20

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wun-Jie Lin ,  Bo-Ting Chen ,  Jen-Chou Tseng ,  Ming-Hsiang Song

IPC分类号： H01L27/10 ,  H01L29/861 ,  H01L21/02 ,  H01L27/02 ,  H01L27/06

CPC分类号： H01L27/0255 ,  H01L27/0629 ,  H01L27/2409 ,  H01L29/66136 ,  H01L29/861

摘要： A structure comprises an N+ region formed over a first fin of a substrate, a P+ region formed over a second fin of the substrate, wherein the P+ region and the N+ region form a diode, a shallow trench isolation region formed between the P+ region and the N+ region and a first epitaxial growth block region formed over the shallow trench isolation region and between the N+ region and the P+ region, wherein a forward bias current of the diode flows through a path underneath the shallow trench isolation region.

摘要翻译： 一种结构包括形成在衬底的第一鳍上的N +区，形成在衬底的第二鳍上的P +区，其中P +区和N +区形成二极管，在P +区和 N +区域和形成在浅沟槽隔离区域之间以及N +区域和P +区域之间的第一外延生长块区域，其中二极管的正向偏置电流流过浅沟槽隔离区域下方的路径。

公开(公告)号：US06979867B2

公开(公告)日：2005-12-27

申请号：US11022730

申请日：2004-12-27

申请人： Yee-Chia Yeo ,  Hao-Yu Chen ,  Hsun-Chih Tsao ,  Fu-Liang Yang ,  Chenming Hu

发明人： Yee-Chia Yeo ,  Hao-Yu Chen ,  Hsun-Chih Tsao ,  Fu-Liang Yang ,  Chenming Hu

IPC分类号： H01L21/762 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L23/58

CPC分类号： H01L21/76264 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78603

摘要： A semiconductor-on-insulator structure includes a substrate and a buried insulator layer overlying the substrate. A plurality of semiconductor islands overlie the buried insulator layer. The semiconductor islands are isolated from one another by trenches. A plurality of recess resistant regions overlie the buried insulator layer at a lower surface of the trenches.

公开(公告)号：US12021033B2

公开(公告)日：2024-06-25

申请号：US17143354

申请日：2021-01-07

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chung-Hui Chen

IPC分类号： H01L23/538 ,  H01L23/50

CPC分类号： H01L23/5384 ,  H01L23/50 ,  H01L23/5385 ,  H01L23/5386

摘要： An integrated circuit (IC) device includes a substrate, a first active region, first and second conductive patterns, and a first through via structure. The substrate has opposite first and second sides. The first active region is over the first side of the substrate. The first conductive pattern is over and electrically coupled to the first active region. The first through via structure extends from the second side, through the substrate, to the first side in electrical contact with the first active region. The second conductive pattern is under the second side of the substrate and electrically coupled to the first through via structure.

公开(公告)号：US20220367286A1

公开(公告)日：2022-11-17

申请号：US17813862

申请日：2022-07-20

申请人： Taiwan Semiconductor Manufacturing, Ltd.

发明人： Chung-Ting Ko ,  Chi On Chui

IPC分类号： H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/45 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/762 ,  H01L21/764 ,  H01L21/285

摘要： A method includes forming a semiconductor fin protruding higher than top surfaces of isolation regions. The isolation regions extend into a semiconductor substrate. The method further includes etching a portion of the semiconductor fin to form a trench, filling the trench with a first dielectric material, wherein the first dielectric material has a first bandgap, and performing a recessing process to recess the first dielectric material. A recess is formed between opposing portions of the isolation regions. The recess is filled with a second dielectric material. The first dielectric material and the second dielectric material in combination form an additional isolation region. The second dielectric material has a second bandgap smaller than the first bandgap.

公开(公告)号：US5804858A

公开(公告)日：1998-09-08

申请号：US721667

申请日：1996-09-27

申请人： Ching-Hsiang Hsu ,  Mong-Song Liang

发明人： Ching-Hsiang Hsu ,  Mong-Song Liang

IPC分类号： H01L21/336 ,  H01L29/786 ,  H01L27/01 ,  H01L29/76

CPC分类号： H01L29/66772 ,  H01L29/7841 ,  H01L29/78612 ,  H01L29/78621

摘要： A new method of forming a silicon-on-insulator device having a body node contact is described. Active areas are isolated from one another within a silicon-on-insulator layer. Adjacent active areas are doped with dopants of opposite polarities to form at least one n-channel active area and at least one p-channel active area. Gate electrodes are formed over each active area. The area directly underlying the gate electrode and extending downward to the insulator layer comprises the body node. Lightly doped areas are formed beneath the spacers on the sidewalls of the gate electrodes. First ions are implanted into the active areas not covered by a mask whereby source and drain regions are formed in the at least one n-channel active area and whereby a p-channel body contact region is formed within the at least one p-channel active area wherein the p-channel body contact region contacts the p-channel body node. Second ions are implanted into the active areas not covered by a mask whereby source and drain regions are formed in the at least one p-channel active area and whereby an n-channel body contact region is formed within the at least one n-channel active area wherein the n-channel body contact region contacts the n-channel body node. The semiconductor substrate is annealed to complete formation of the silicon-on-insulator device having a body node contact in the manufacture of an integrated circuit.

摘要翻译： 描述了形成具有身体节点接触的绝缘体上硅器件的新方法。 有源区域在绝缘体上硅层内彼此隔离。 相邻有源区掺杂有相反极性的掺杂剂以形成至少一个n沟道有源区和至少一个p沟道有源区。 在每个有效区域上形成栅电极。 栅电极正下方并向下延伸至绝缘体层的区域包括主体节点。 在栅电极的侧壁上的间隔物下方形成轻掺杂区域。 将第一离子注入到未被掩模覆盖的有源区中，由此在至少一个n沟道有源区中形成源区和漏区，由此在至少一个p沟道活性区内形成p沟道体接触区 其中所述p沟道体接触区域与所述p沟道体节点接触。 将第二离子注入到未被掩模覆盖的有源区中，从而在至少一个p沟道有源区中形成源区和漏区，由此在至少一个n沟道活性区内形成n沟体体接触区 其中所述n通道体接触区域与所述n通道体节点接触。 半导体衬底被退火以在集成电路的制造中完成具有体节点接触的绝缘体上硅器件的形成。