Invention Grant
- Patent Title: Uniform gate width for nanostructure devices
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Application No.: US17728247Application Date: 2022-04-25
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Publication No.: US11855096B2Publication Date: 2023-12-26
- Inventor: Jui-Chien Huang , Shih-Cheng Chen , Chih-Hao Wang , Kuo-Cheng Chiang , Zhi-Chang Lin , Jung-Hung Chang , Lo-Heng Chang , Shi Ning Ju , Guan-Lin Chen
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
- Current Assignee Address: TW Hsinchu
- Agency: HAYNES AND BOONE, LLP
- Main IPC: H01L27/092
- IPC: H01L27/092 ; H01L29/06 ; H01L29/66 ; H01L29/78 ; H01L21/8234

Abstract:
According to one example, a semiconductor device includes a substrate and a fin stack that includes a plurality of nanostructures, a gate device surrounding each of the nanostructures, and inner spacers along the gate device and between the nanostructures. A width of the inner spacers differs between different layers of the fin stack.
Public/Granted literature
- US20220246614A1 Uniform Gate Width For Nanostructure Devices Public/Granted day:2022-08-04
Information query
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