公开(公告)号：US11532626B2

公开(公告)日：2022-12-20

申请号：US16888537

申请日：2020-05-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Hung Chang ,  Lo-Heng Chang ,  Zhi-Chang Lin ,  Shih-Cheng Chen ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC: H01L29/78 ,  H01L27/092 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/66 ,  H01L29/10

Abstract: A semiconductor device according to the present disclosure includes a bottom dielectric feature on a substrate, a plurality of channel members directly over the bottom dielectric feature, a gate structure wrapping around each of the plurality of channel members, two first epitaxial features sandwiching the bottom dielectric feature along a first direction, and two second epitaxial features sandwiching the plurality of channel members along the first direction.

公开(公告)号：US11417777B2

公开(公告)日：2022-08-16

申请号：US16898717

申请日：2020-06-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lo-Heng Chang ,  Jung-Hung Chang ,  Zhi-Chang Lin ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L21/308 ,  H01L21/8234 ,  H01L29/786 ,  H01L29/66 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/02

Abstract: A method of forming a semiconductor device includes forming a fin of alternating layers of semiconductor nanostructures and sacrificial layers, laterally etching sidewall portions of the sacrificial layers, and depositing additional semiconductor material over the sidewalls of the semiconductor nanostructures and sacrificial layers. Following deposition of a dielectric material over the additional semiconductor material and additional etching, the remaining portions of the semiconductor structures and additional semiconductor material collectively form a hammer shape at each opposing side of the fin. Epitaxial source/drain regions formed on the opposing sides of the fin will contact the heads of the hammer shapes.

公开(公告)号：US11315925B2

公开(公告)日：2022-04-26

申请号：US16932476

申请日：2020-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jui-Chien Huang ,  Shih-Cheng Chen ,  Chih-Hao Wang ,  Kuo-Cheng Chiang ,  Zhi-Chang Lin ,  Jung-Hung Chang ,  Lo-Heng Chang ,  Shi Ning Ju ,  Guan-Lin Chen

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234

Abstract: According to one example, a semiconductor device includes a substrate and a fin stack that includes a plurality of nanostructures, a gate device surrounding each of the nanostructures, and inner spacers along the gate device and between the nanostructures. A width of the inner spacers differs between different layers of the fin stack.

公开(公告)号：US11264502B2

公开(公告)日：2022-03-01

申请号：US16803278

申请日：2020-02-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Hung Chang ,  Lo-Heng Chang ,  Zhi-Chang Lin ,  Shih-Cheng Chen ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC: H01L21/3065 ,  H01L27/092 ,  H01L29/66 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/308 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/311

Abstract: A method of independently forming source/drain regions in NMOS regions including nanosheet field-effect transistors (NSFETs), NMOS regions including fin field-effect transistors (FinFETs) PMOS regions including NSFETs, and PMOS regions including FinFETs and semiconductor devices formed by the method are disclosed. In an embodiment, a device includes a semiconductor substrate; a first nanostructure over the semiconductor substrate; a first epitaxial source/drain region adjacent the first nanostructure; a first inner spacer layer adjacent the first epitaxial source/drain region, the first inner spacer layer comprising a first material; a second nanostructure over the semiconductor substrate; a second epitaxial source/drain region adjacent the second nanostructure; and a second inner spacer layer adjacent the second epitaxial source/drain region, the second inner spacer layer comprising a second material different from the first material.

公开(公告)号：US20210126113A1

公开(公告)日：2021-04-29

申请号：US16872058

申请日：2020-05-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zhi-Chang Lin ,  Shih-Cheng Chen ,  Lo-Heng Chang ,  Jung-Hung Chang ,  Kuo-Cheng Chiang

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L21/8234

Abstract: Semiconductor devices using a dielectric structure and methods of manufacturing are described herein. The semiconductor devices are directed towards gate-all-around (GAA) devices that are formed over a substrate and are isolated from one another by the dielectric structure. The dielectric structure is formed over the fin between two GAA devices and cuts a gate electrode that is formed over the fin into two separate gate electrodes. The two GAA devices are also formed with bottom spacers underlying source/drain regions of the GAA devices. The bottom spacers isolate the source/drain regions from the substrate. The dielectric structure is formed with a shallow bottom that is located above the bottoms of the bottom spacers.

公开(公告)号：US11996482B2

公开(公告)日：2024-05-28

申请号：US18120879

申请日：2023-03-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Zhi-Chang Lin ,  Shih-Cheng Chen ,  Jung-Hung Chang ,  Lo-Heng Chang ,  Chien-Ning Yao

IPC: H01L29/786 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/78609 ,  H01L21/02603 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: A device includes a semiconductor substrate, a channel layer, a gate structure, source/drain epitaxial structures, and a dielectric isolation layer. The channel layer is over the semiconductor substrate. The gate structure is over the semiconductor substrate and surrounds the channel layer. The source/drain epitaxial structures are connected to the channel layer and arranged in a first direction. The dielectric isolation layer is between the gate structure and the semiconductor substrate. The dielectric isolation layer is wider than the gate structure but narrower than the channel layer in the first direction.

公开(公告)号：US11929287B2

公开(公告)日：2024-03-12

申请号：US17238376

申请日：2021-04-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zhi-Chang Lin ,  Shih-Cheng Chen ,  Kuo-Cheng Chiang ,  Kuan-Ting Pan ,  Jung-Hung Chang ,  Lo-Heng Chang ,  Chien Ning Yao

IPC: H01L21/8234 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L21/823468 ,  H01L29/42392 ,  H01L29/78696

Abstract: The present disclosure describes a semiconductor structure with a dielectric liner. The semiconductor structure includes a substrate and a fin structure on the substrate. The fin structure includes a stacked fin structure, a fin bottom portion below the stacked fin structure, and an isolation layer between the stacked fin structure and the bottom fin portion. The semiconductor structure further includes a dielectric liner in contact with an end of the stacked fin structure and a spacer structure in contact with the dielectric liner.

公开(公告)号：US11502034B2

公开(公告)日：2022-11-15

申请号：US17027344

申请日：2020-09-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Lo-Heng Chang ,  Kuo-Cheng Chiang ,  Zhi-Chang Lin ,  Jung-Hung Chang ,  Shih-Cheng Chen ,  Shi-Ning Ju ,  Chih-Hao Wang

IPC: H01L23/528 ,  H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L21/8234 ,  H01L21/8238

Abstract: Corner portions of a semiconductor fin are kept on the device while removing a semiconductor fin prior to forming a backside contact. The corner portions of the semiconductor fin protect source/drain regions from etchant during backside processing. The corner portions allow the source/drain features to be formed with a convex profile on the backside. The convex profile increases volume of the source/drain features, thus, improving device performance. The convex profile also increases processing window of backside contact recess formation.

公开(公告)号：US20210375864A1

公开(公告)日：2021-12-02

申请号：US16888537

申请日：2020-05-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Hung Chang ,  Lo-Heng Chang ,  Zhi-Chang Lin ,  Shih-Cheng Chen ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/08

Abstract: A semiconductor device according to the present disclosure includes a bottom dielectric feature on a substrate, a plurality of channel members directly over the bottom dielectric feature, a gate structure wrapping around each of the plurality of channel members, two first epitaxial features sandwiching the bottom dielectric feature along a first direction, and two second epitaxial features sandwiching the plurality of channel members along the first direction.

公开(公告)号：US11121037B2

公开(公告)日：2021-09-14

申请号：US16586523

申请日：2019-09-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Wei Tsai ,  Yu-Xuan Huang ,  Kuan-Lun Cheng ,  Chih-Hao Wang ,  Min Cao ,  Jung-Hung Chang ,  Lo-Heng Chang ,  Pei-Hsun Wang ,  Kuo-Cheng Chiang

IPC: H01L21/8234 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/02

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first gate stack and a second gate stack over a substrate. The substrate has a base, a first fin structure, and a second fin structure over the base, the second fin structure is wider than the first fin structure. The method includes partially removing the first fin structure, which is not covered by the first gate stack, and the second fin structure, which is not covered by the second gate stack. The method includes forming an inner spacer layer over the first fin structure, which is not covered by the first gate stack. The method includes forming a first stressor and a second stressor respectively over the inner spacer layer and the second fin structure, which is not covered by the second gate stack.