公开(公告)号：US20240413019A1

公开(公告)日：2024-12-12

申请号：US18402166

申请日：2024-01-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Yun Wu ,  Jui-Chien Huang ,  Szuya Liao

IPC: H01L21/8238 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

Abstract: A method includes forming a first transistor in a first wafer, wherein the first transistor includes a first source/drain region, forming a first bond pad electrically coupling to the first source/drain region, forming an second transistor in a second wafer, wherein the second transistor includes a second source/drain region, forming a second bond pad electrically coupling to the second source/drain region, and bonding the second wafer to the first wafer, with the second bond pad being bonded to the first bond pad.

公开(公告)号：US12148812B2

公开(公告)日：2024-11-19

申请号：US17814952

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jui-Chien Huang ,  Kuo-Cheng Chiang ,  Chih-Hao Wang ,  Shi Ning Ju ,  Guan-Lin Chen

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L29/08

Abstract: A device includes a first channel layer over a semiconductor substrate, a second channel layer over the first channel layer, and a third channel layer over the second channel layer. The channel layers each connects a first and a second source/drain along a first direction. The device also includes a first gate portion between the first and second channel layers; a second gate portion between the second and third channel layers; a first inner spacer between the first and second channel layers and between the first gate portion and the first source/drain; and a second inner spacer between the second and third channel layers and between the second gate portion and the first source/drain. The first and second gate portions have substantially the same gate lengths along the first direction. The first inner spacer has a width along the first direction that is greater than the second inner spacer has.

公开(公告)号：US20240347391A1

公开(公告)日：2024-10-17

申请号：US18752112

申请日：2024-06-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Guan-Lin Chen ,  Chih-Hao Wang ,  Ching-Wei Tsai ,  Shi Ning Ju ,  Jui-Chien Huang ,  Kuo-Cheng Chiang ,  Kuan-Lun Cheng

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/28 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L21/823828 ,  H01L21/02603 ,  H01L21/28123 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: Self-aligned gate cutting techniques for multigate devices are disclosed herein that provide multigate devices having asymmetric metal gate profiles and asymmetric source/drain feature profiles. An exemplary multigate device has a channel layer, a metal gate that wraps a portion of the channel layer, and source/drain features disposed over a substrate. The channel layer extends along a first direction between the source/drain features. A first dielectric fin and a second dielectric fin are disposed over the substrate and configured differently. The channel layer extends along a second direction between the first dielectric fin and the second dielectric fin. The metal gate is disposed between the channel layer and the second dielectric fin. In some embodiments, the first dielectric fin is disposed on a first isolation feature, and the second dielectric fin is disposed on a second isolation feature. The first isolation feature and the second isolation feature are configured differently.

公开(公告)号：US12009216B2

公开(公告)日：2024-06-11

申请号：US18358152

申请日：2023-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hsiung Lin ,  Shih-Cheng Chen ,  Chih-Hao Wang ,  Jung-Hung Chang ,  Jui-Chien Huang

IPC: H01L21/285 ,  H01L21/02 ,  H01L21/311 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L21/28518 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/31111 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: A semiconductor structure includes a semiconductor fin extending from a substrate, a source/drain (S/D) feature disposed over the semiconductor fin, a silicide layer disposed over the S/D feature, where the silicide layer extends along a sidewall of the S/D feature, and an etch-stop layer (ESL) disposed along a sidewall of the silicide layer.

公开(公告)号：US20220238341A1

公开(公告)日：2022-07-28

申请号：US17722582

申请日：2022-04-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hsiung Lin ,  Shih-Cheng Chen ,  Chih-Hao Wang ,  Jung-Hung Chang ,  Jui-Chien Huang

IPC: H01L21/285 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L21/311

Abstract: A semiconductor structure includes a semiconductor fin extending from a substrate, a source/drain (S/D) feature disposed over the semiconductor fin, a silicide layer disposed over the S/D feature, where the silicide layer extends along a sidewall of the S/D feature, and an etch-stop layer (ESL) disposed along a sidewall of the silicide layer.

公开(公告)号：US20220037509A1

公开(公告)日：2022-02-03

申请号：US16941504

申请日：2020-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jui-Chien Huang ,  Kuo-Cheng Chiang ,  Chih-Hao Wang ,  Shi Ning Ju ,  Guan-Lin Chen

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/423

Abstract: A device includes a first channel layer over a semiconductor substrate, a second channel layer over the first channel layer, and a third channel layer over the second channel layer. The channel layers each connects a first and a second source/drain along a first direction. The device also includes a first gate portion between the first and second channel layers; a second gate portion between the second and third channel layers; a first inner spacer between the first and second channel layers and between the first gate portion and the first source/drain; and a second inner spacer between the second and third channel layers and between the second gate portion and the first source/drain. The first and second gate portions have substantially the same gate lengths along the first direction. The first inner spacer has a width along the first direction that is greater than the second inner spacer has.

公开(公告)号：US20200105617A1

公开(公告)日：2020-04-02

申请号：US16366946

申请日：2019-03-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hao Wang ,  Jui-Chien Huang ,  Chun-Hsiung Lin ,  Kuo-Cheng Chiang ,  Chih-Chao Chou ,  Pei-Hsun Wang

IPC: H01L21/8238 ,  H01L21/306 ,  H01L29/06 ,  H01L21/02 ,  H01L21/324 ,  H01L29/423 ,  H01L27/092 ,  H01L29/08 ,  H01L29/10

Abstract: A method that includes forming first semiconductor layers and second semiconductor layers disposed over a substrate, wherein the first and second semiconductor layers have different material compositions, are alternatingly disposed, and extend over first and second regions of the substrate; patterning the first and the second semiconductor layers to form a first fin in the first region and a second fin in the second region; removing the first semiconductor layers from the first and second fins such that a first portion of the patterned second semiconductor layers becomes first suspended nanostructures in the first fin and that a second portion of the patterned second semiconductor layers becomes second suspended nanostructures in the second fin; forming third semiconductor layers on the second suspended nanostructures in the second fin; and performing an anneal process to drive materials contained in the third semiconductor layers into corresponding second suspended nanostructures in the second fin.

公开(公告)号：US20230345693A1

公开(公告)日：2023-10-26

申请号：US18163746

申请日：2023-02-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Yin WANG ,  Szuya Liao ,  Jui-Chien Huang

IPC: H10B10/00

CPC classification number: H10B10/125

Abstract: An integrated circuit includes a plurality of SRAM cells. Each SRAM cell includes a first inverter having a first N-type transistor and a first P-type transistor stacked vertically in a first active region. The SRAM cell includes a second inverter cross-coupled with the first inverter and including a second N-type transistor and a second P-type transistor stacked vertically in a second active region. The SRAM cell includes a butt contact electrically connecting an output of the first inverter to an input of the second inverter. The butt contact is at least partially within a first active region.

公开(公告)号：US11695076B2

公开(公告)日：2023-07-04

申请号：US17193732

申请日：2021-03-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Hsun Wang ,  Chih-Chao Chou ,  Shih-Cheng Chen ,  Jung-Hung Chang ,  Jui-Chien Huang ,  Chun-Hsiung Lin ,  Chih-Hao Wang

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L21/02 ,  H01L21/285

CPC classification number: H01L29/78618 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/28518 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/78684 ,  H01L29/78696

Abstract: The present disclosure provides a semiconductor device that includes a semiconductor fin disposed over a substrate, an isolation structure at least partially surrounding the fin, an epitaxial source/drain (S/D) feature disposed over the semiconductor fin, where an extended portion of the epitaxial S/D feature extends over the isolation structure, and a silicide layer disposed on the epitaxial S/D feature, where the silicide layer covers top, bottom, sidewall, front, and back surfaces of the extended portion of the S/D feature.

公开(公告)号：US20230145872A1

公开(公告)日：2023-05-11

申请号：US18066141

申请日：2022-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Hsun Wang ,  Chih-Chao Chou ,  Shih-Cheng Chen ,  Jung-Hung Chang ,  Jui-Chien Huang ,  Chun-Hsiung Lin ,  Chih-Hao Wang

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L21/02 ,  H01L21/285

CPC classification number: H01L29/78618 ,  H01L29/0673 ,  H01L29/0653 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/66742 ,  H01L29/78696 ,  H01L21/02603 ,  H01L21/02532 ,  H01L21/28518 ,  H01L29/66545 ,  H01L29/78684

Abstract: The present disclosure provides a semiconductor device that includes a semiconductor fin disposed over a substrate, an isolation structure at least partially surrounding the fin, an epitaxial source/drain (S/D) feature disposed over the semiconductor fin, where an extended portion of the epitaxial S/D feature extends over the isolation structure, and a silicide layer disposed on the epitaxial S/D feature, where the silicide layer covers top, bottom, sidewall, front, and back surfaces of the extended portion of the S/D feature.