Invention Grant
- Patent Title: Package structure with solder resist underlayer for warpage control and method of manufacturing the same
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Application No.: US16718213Application Date: 2019-12-18
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Publication No.: US11862594B2Publication Date: 2024-01-02
- Inventor: Ting-Chen Tseng , Hung-Jui Kuo , Yu-Hsiang Hu , Sih-Hao Liao
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: JCIPRNET
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L23/522 ; H01L23/00 ; H01L23/31 ; H01L23/495 ; H01L23/528 ; H01L23/532 ; H01L23/367 ; H01L25/065 ; H01L23/28 ; H01L21/56

Abstract:
A package structure includes a semiconductor die, conductive pillars, an insulating encapsulation, a redistribution circuit structure, and a solder resist layer. The conductive pillars are arranged aside of the semiconductor die. The insulating encapsulation encapsulates the semiconductor die and the conductive pillars, and the insulating encapsulation has a first surface and a second surface opposite to the first surface. The redistribution circuit structure is located on the first surface of the insulating encapsulation. The solder resist layer is located on the second surface of the insulating encapsulation, wherein a material of the solder resist layer includes a filler.
Public/Granted literature
- US20210193605A1 PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME Public/Granted day:2021-06-24
Information query
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