公开(公告)号：US20250133812A1

公开(公告)日：2025-04-24

申请号：US19002409

申请日：2024-12-26

Applicant: Taiwan Semiconductor Manufacturing Co, Ltd.

Inventor： Meng-Che Tu ,  Wei-Chih Chen ,  Sih-Hao Liao ,  Yu-Hsiang Hu ,  Hung-Jui Kuo ,  Chen-Hua Yu

IPC: H10D84/01 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

Abstract: A method of forming a semiconductor device includes forming a first dielectric layer over a front side of a wafer, the wafer having a plurality of dies at the front side of the wafer, the first dielectric layer having a first shrinkage ratio smaller than a first pre-determined threshold; curing the first dielectric layer at a first temperature, where after curing the first dielectric layer, a first distance between a highest point of an upper surface of the first dielectric layer and a lowest point of the upper surface of the first dielectric layer is smaller than a second pre-determined threshold; thinning the wafer from a backside of the wafer; and performing a dicing process to separate the plurality of dies into individual dies.

公开(公告)号：US12265330B2

公开(公告)日：2025-04-01

申请号：US18446562

申请日：2023-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sih-Hao Liao ,  Yu-Hsiang Hu ,  Hung-Jui Kuo ,  Chen-Hua Yu

IPC: G03F7/031 ,  C08G73/10 ,  G03F7/038 ,  G03F7/039 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/18 ,  H01L21/56

Abstract: A method of manufacturing a semiconductor device includes applying a polymer mixture over a substrate, exposing and developing at least a portion of the polymer mixture to form a developed dielectric, and curing the developed dielectric to form a dielectric layer. The polymer mixture includes a polymer precursor, a photosensitizer, and a solvent. The polymer precursor may be a polyamic acid ester.

公开(公告)号：US12191222B2

公开(公告)日：2025-01-07

申请号：US18335294

申请日：2023-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Chih Chen ,  Sih-Hao Liao ,  Yu-Hsiang Hu ,  Hung-Jui Kuo

IPC: H01L23/31 ,  H01L23/498

Abstract: A redistribution structure is made using filler-free insulating materials with a high shrinkage rate. As a result, good planarity may be achieved without the need to perform a planarization of each insulating layer of the redistribution structure, thereby simplifying the formation of the redistribution structure.

公开(公告)号：US12165985B2

公开(公告)日：2024-12-10

申请号：US17818625

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Hui-Jung Tsai ,  Hung-Jui Kuo ,  Chung-Shi Liu ,  Han-Ping Pu ,  Ting-Chu Ko

IPC: H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538

Abstract: In accordance with some embodiments a via is formed over a semiconductor device, wherein the semiconductor device is encapsulated within an encapsulant 129. A metallization layer and a second via are formed over and in electrical connection with the first via, and the metallization layer and the second via are formed using the same seed layer. Embodiments include fully landed vias, partially landed vias in contact with the seed layer, and partially landed vias not in contact with the seed layer.

公开(公告)号：US12020983B2

公开(公告)日：2024-06-25

申请号：US18302545

申请日：2023-04-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun Chen Hsieh ,  Hui-Jung Tsai ,  Hung-Jui Kuo ,  Chen-Hua Yu

IPC: H01L21/00 ,  H01L21/3213 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76871 ,  H01L21/32139 ,  H01L21/565 ,  H01L21/76856 ,  H01L23/3107 ,  H01L23/5226 ,  H01L23/53238 ,  H01L24/09 ,  H01L24/14 ,  H01L24/17 ,  H01L24/32 ,  H01L2224/02379

Abstract: A method includes forming a metal seed layer on a dielectric layer, and forming a patterned mask over the metal seed layer. An opening in the patterned mask is over a first portion of the dielectric layer, and the patterned mask overlaps a second portion of the dielectric layer. The method further includes plating a metal region in the opening, removing the patterned mask to expose portions of the metal seed layer, etching the exposed portions of the metal seed layer, performing a plasma treatment on a surface of the second portion of the dielectric layer, and performing an etching process on the surface of the second portion of the dielectric layer.

公开(公告)号：US20240194611A1

公开(公告)日：2024-06-13

申请号：US18587407

申请日：2024-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Han Wang ,  Hung-Jui Kuo ,  Yu-Hsiang Hu

IPC: H01L23/538 ,  H01L21/288 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/50 ,  H01L25/00 ,  H01L25/065 ,  H01L25/10 ,  H01L25/16

CPC classification number: H01L23/5389 ,  H01L21/2885 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/56 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76873 ,  H01L21/76879 ,  H01L23/3128 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/19 ,  H01L24/24 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L23/50 ,  H01L25/0657 ,  H01L2221/68331 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/211 ,  H01L2224/24265 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/06586 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19011 ,  H01L2924/19102

Abstract: In an embodiment, a device includes: a molding compound; an integrated circuit die encapsulated in the molding compound; a through via adjacent the integrated circuit die; and a redistribution structure over the integrated circuit die, the molding compound, and the through via, the redistribution structure electrically connected to the integrated circuit die and the through via, the redistribution structure including: a first dielectric layer disposed over the molding compound; a first conductive via extending through the first dielectric layer; a second dielectric layer disposed over the first dielectric layer and the first conductive via; and a second conductive via extending through the second dielectric layer and into a portion of the first conductive via, an interface between the first conductive via and the second conductive via being non-planar.

公开(公告)号：US20240088056A1

公开(公告)日：2024-03-14

申请号：US18510091

申请日：2023-11-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jhih-Yu Wang ,  Yung-Chi Chu ,  Sih-Hao Liao ,  Yu-Hsiang Hu ,  Hung-Jui Kuo

IPC: H01L23/544 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L25/00 ,  H01L25/10

CPC classification number: H01L23/544 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L25/50 ,  H01L2223/54426 ,  H01L2224/214 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1082

Abstract: A method includes encapsulating a device die in an encapsulating material, forming a first dielectric layer over the device die and the encapsulating material, forming first redistribution lines extending into the first dielectric layer to electrically couple to the device die, forming an alignment mark over the first dielectric layer, wherein the alignment mark includes a plurality of elongated strips, forming a second dielectric layer over the first redistribution lines and the alignment mark, and forming second redistribution lines extending into the second dielectric layer to electrically couple to the first redistribution lines. The second redistribution lines are formed using the alignment mark for alignment.

公开(公告)号：US20230386955A1

公开(公告)日：2023-11-30

申请号：US18447416

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Chen Tseng ,  Sih-Hao Liao ,  Yu-Hsiang Hu ,  Hung-Jui Kuo

IPC: H01L23/31 ,  H01L23/00 ,  H01L21/311 ,  H01L21/56

CPC classification number: H01L23/3185 ,  H01L24/20 ,  H01L21/31133 ,  H01L24/19 ,  H01L21/56 ,  H01L2224/221

Abstract: A package and a method forming the same are provided. The package includes an integrated circuit die. A sidewall of the integrated circuit die has a first facet and a second facet. The first facet and the second facet have different slopes. The package includes an encapsulant surrounding the integrated circuit die and in physical contact with the first facet and the second facet and an insulating layer over the integrated circuit die and the encapsulant. An upper surface of the integrated circuit die is lower than an upper surface of the encapsulant. A sidewall of the insulating layer is substantially coplanar with the first facet.

公开(公告)号：US11817352B2

公开(公告)日：2023-11-14

申请号：US17409010

申请日：2021-08-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Han Wang ,  Yu-Hsiang Hu ,  Hung-Jui Kuo

IPC: H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/31 ,  H01L21/56 ,  H01L23/532

CPC classification number: H01L21/76898 ,  H01L21/563 ,  H01L21/76873 ,  H01L21/76885 ,  H01L23/3171 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/5329 ,  H01L24/09 ,  H01L2224/0231 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/02381

Abstract: A method of fabricating a redistribution circuit structure including the following steps is provided. A conductive via is formed. A photosensitive dielectric layer is formed to cover the conductive via. The photosensitive dielectric layer is partially removed to reveal the conductive via at least through an exposure and development process. A redistribution wiring is formed on the photosensitive dielectric layer and the revealed conductive via.

公开(公告)号：US20230326822A1

公开(公告)日：2023-10-12

申请号：US18335294

申请日：2023-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Chih Chen ,  Sih-Hao Liao ,  Yu-Hsiang Hu ,  Hung-Jui Kuo

IPC: H01L23/31 ,  H01L23/498

CPC classification number: H01L23/3178 ,  H01L23/49822 ,  H01L23/49861 ,  H01L23/3192

Abstract: A redistribution structure is made using filler-free insulating materials with a high shrinkage rate. As a result, good planarity may be achieved without the need to perform a planarization of each insulating layer of the redistribution structure, thereby simplifying the formation of the redistribution structure.