公开(公告)号：US20230386955A1

公开(公告)日：2023-11-30

申请号：US18447416

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Chen Tseng ,  Sih-Hao Liao ,  Yu-Hsiang Hu ,  Hung-Jui Kuo

IPC: H01L23/31 ,  H01L23/00 ,  H01L21/311 ,  H01L21/56

CPC classification number: H01L23/3185 ,  H01L24/20 ,  H01L21/31133 ,  H01L24/19 ,  H01L21/56 ,  H01L2224/221

Abstract: A package and a method forming the same are provided. The package includes an integrated circuit die. A sidewall of the integrated circuit die has a first facet and a second facet. The first facet and the second facet have different slopes. The package includes an encapsulant surrounding the integrated circuit die and in physical contact with the first facet and the second facet and an insulating layer over the integrated circuit die and the encapsulant. An upper surface of the integrated circuit die is lower than an upper surface of the encapsulant. A sidewall of the insulating layer is substantially coplanar with the first facet.

公开(公告)号：US20230386906A1

公开(公告)日：2023-11-30

申请号：US18446521

申请日：2023-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Chen Tseng ,  Sih-Hao Liao ,  Po-Han Wang ,  Yu-Hsiang Hu ,  Hung-Jui Kuo

IPC: H01L21/768 ,  H01L21/22 ,  H01L23/498 ,  H01L23/538 ,  H01L21/48 ,  H01L23/48

CPC classification number: H01L21/76822 ,  H01L21/22 ,  H01L21/76838 ,  H01L23/49822 ,  H01L23/49827 ,  H01L21/31144 ,  H01L23/49833 ,  H01L21/4857 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/5389

Abstract: In an embodiment, a method includes: dispensing a first dielectric layer around and on a first metallization pattern, the first dielectric layer including a photoinsensitive molding compound; planarizing the first dielectric layer such that surfaces of the first dielectric layer and the first metallization pattern are planar; forming a second metallization pattern on the first dielectric layer and the first metallization pattern; dispensing a second dielectric layer around the second metallization pattern and on the first dielectric layer, the second dielectric layer including a photosensitive molding compound; patterning the second dielectric layer with openings exposing portions of the second metallization pattern; and forming a third metallization pattern on the second dielectric layer and in the openings extending through the second dielectric layer, the third metallization pattern coupled to the portions of the second metallization pattern exposed by the openings.

公开(公告)号：US12009226B2

公开(公告)日：2024-06-11

申请号：US17458663

申请日：2021-08-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Chen Tseng ,  Sih-Hao Liao ,  Yu-Hsiang Hu ,  Hung-Jui Kuo

IPC: H01L23/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/29 ,  H01L23/31

CPC classification number: H01L21/56 ,  H01L23/293 ,  H01L23/3157 ,  H01L24/05 ,  H01L24/19 ,  H01L24/20 ,  H01L24/97 ,  H01L2224/2101 ,  H01L2924/37001

Abstract: A method includes attaching an integrated circuit die adjacent to a first substrate, the integrated circuit die comprising: an active device in a second substrate; a pad adjacent to the second substrate; and a first dielectric layer adjacent to the second substrate, the first dielectric layer comprising a polyimide with an ester group; forming an encapsulant around the integrated circuit die; and removing the first dielectric layer.

公开(公告)号：US20220310467A1

公开(公告)日：2022-09-29

申请号：US17333399

申请日：2021-05-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Chen Tseng ,  Sih-Hao Liao ,  Yu-Hsiang Hu ,  Hung-Jui Kuo

IPC: H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L21/311

Abstract: A package and a method forming the same are provided. The package includes an integrated circuit die. A sidewall of the integrated circuit die has a first facet and a second facet. The first facet and the second facet have different slopes. The package includes an encapsulant surrounding the integrated circuit die and in physical contact with the first facet and the second facet and an insulating layer over the integrated circuit die and the encapsulant. An upper surface of the integrated circuit die is lower than an upper surface of the encapsulant. A sidewall of the insulating layer is substantially coplanar with the first facet.

公开(公告)号：US20240387310A1

公开(公告)日：2024-11-21

申请号：US18788697

申请日：2024-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Chen Tseng ,  Sih-Hao Liao ,  Yu-Hsiang Hu ,  Hung-Jui Kuo

IPC: H01L23/31 ,  H01L21/311 ,  H01L21/56 ,  H01L23/00

Abstract: A package and a method forming the same are provided. The package includes an integrated circuit die. A sidewall of the integrated circuit die has a first facet and a second facet. The first facet and the second facet have different slopes. The package includes an encapsulant surrounding the integrated circuit die and in physical contact with the first facet and the second facet and an insulating layer over the integrated circuit die and the encapsulant. An upper surface of the integrated circuit die is lower than an upper surface of the encapsulant. A sidewall of the insulating layer is substantially coplanar with the first facet.

公开(公告)号：US20240297053A1

公开(公告)日：2024-09-05

申请号：US18656346

申请日：2024-05-06

Applicant: Taiwan Semiconductor Manufacturing Co, Ltd.

Inventor： Ting-Chen Tseng ,  Sih-Hao Liao ,  Yu-Hsiang Hu ,  Hung-Jui Kuo

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/29 ,  H01L23/31

CPC classification number: H01L21/56 ,  H01L23/293 ,  H01L23/3157 ,  H01L24/05 ,  H01L24/19 ,  H01L24/20 ,  H01L24/97 ,  H01L2224/2101 ,  H01L2924/37001

Abstract: A method includes attaching an integrated circuit die adjacent to a first substrate, the integrated circuit die comprising: an active device in a second substrate; a pad adjacent to the second substrate; and a first dielectric layer adjacent to the second substrate, the first dielectric layer comprising a polyimide with an ester group; forming an encapsulant around the integrated circuit die; and removing the first dielectric layer.

公开(公告)号：US11862594B2

公开(公告)日：2024-01-02

申请号：US16718213

申请日：2019-12-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Chen Tseng ,  Hung-Jui Kuo ,  Yu-Hsiang Hu ,  Sih-Hao Liao

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L23/528 ,  H01L23/532 ,  H01L23/367 ,  H01L25/065 ,  H01L23/28 ,  H01L21/56

CPC classification number: H01L24/14 ,  H01L21/561 ,  H01L23/28 ,  H01L23/4952 ,  H01L23/528 ,  H01L23/5226 ,  H01L24/94

Abstract: A package structure includes a semiconductor die, conductive pillars, an insulating encapsulation, a redistribution circuit structure, and a solder resist layer. The conductive pillars are arranged aside of the semiconductor die. The insulating encapsulation encapsulates the semiconductor die and the conductive pillars, and the insulating encapsulation has a first surface and a second surface opposite to the first surface. The redistribution circuit structure is located on the first surface of the insulating encapsulation. The solder resist layer is located on the second surface of the insulating encapsulation, wherein a material of the solder resist layer includes a filler.

公开(公告)号：US11854927B2

公开(公告)日：2023-12-26

申请号：US17333399

申请日：2021-05-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Chen Tseng ,  Sih-Hao Liao ,  Yu-Hsiang Hu ,  Hung-Jui Kuo

IPC: H01L23/31 ,  H01L23/00 ,  H01L21/311 ,  H01L21/56

CPC classification number: H01L23/3185 ,  H01L21/31133 ,  H01L21/56 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/221

Abstract: A package and a method forming the same are provided. The package includes an integrated circuit die. A sidewall of the integrated circuit die has a first facet and a second facet. The first facet and the second facet have different slopes. The package includes an encapsulant surrounding the integrated circuit die and in physical contact with the first facet and the second facet and an insulating layer over the integrated circuit die and the encapsulant. An upper surface of the integrated circuit die is lower than an upper surface of the encapsulant. A sidewall of the insulating layer is substantially coplanar with the first facet.

公开(公告)号：US20230063181A1

公开(公告)日：2023-03-02

申请号：US17458663

申请日：2021-08-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Chen Tseng ,  Sih-Hao Liao ,  Yu-Hsiang Hu ,  Hung-Jui Kuo

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/29 ,  H01L23/31

Abstract: A method includes attaching an integrated circuit die adjacent to a first substrate, the integrated circuit die comprising: an active device in a second substrate; a pad adjacent to the second substrate; and a first dielectric layer adjacent to the second substrate, the first dielectric layer comprising a polyimide with an ester group; forming an encapsulant around the integrated circuit die; and removing the first dielectric layer.

公开(公告)号：US20210193605A1

公开(公告)日：2021-06-24

申请号：US16718213

申请日：2019-12-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Chen Tseng ,  Hung-Jui Kuo ,  Yu-Hsiang Hu ,  Sih-Hao Liao

IPC: H01L23/00 ,  H01L23/495 ,  H01L23/28 ,  H01L23/522 ,  H01L23/528 ,  H01L21/56

Abstract: A package structure includes a semiconductor die, conductive pillars, an insulating encapsulation, a redistribution circuit structure, and a solder resist layer. The conductive pillars are arranged aside of the semiconductor die. The insulating encapsulation encapsulates the semiconductor die and the conductive pillars, and the insulating encapsulation has a first surface and a second surface opposite to the first surface. The redistribution circuit structure is located on the first surface of the insulating encapsulation. The solder resist layer is located on the second surface of the insulating encapsulation, wherein a material of the solder resist layer includes a filler.