Invention Grant
- Patent Title: Multi-chip package and method of providing die-to-die interconnects in same
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Application No.: US17144130Application Date: 2021-01-07
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Publication No.: US11876053B2Publication Date: 2024-01-16
- Inventor: Henning Braunisch , Chia-Pin Chiu , Aleksandar Aleksov , Hinmeng Au , Stefanie M. Lotz , Johanna M. Swan , Sujit Sharan
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- The original application number of the division: US15876080 2018.01.19
- Main IPC: H01L23/538
- IPC: H01L23/538 ; H01L23/13 ; H01L23/00 ; H01L25/065 ; H01L21/683

Abstract:
A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).
Public/Granted literature
- US20210134726A1 MULTI-CHIP PACKAGE AND METHOD OF PROVIDING DIE-TO-DIE INTERCONNECTS IN SAME Public/Granted day:2021-05-06
Information query
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