Invention Grant
- Patent Title: Packed 16 bits instruction pipeline
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Application No.: US15799560Application Date: 2017-10-31
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Publication No.: US11880683B2Publication Date: 2024-01-23
- Inventor: Jiasheng Chen , Bin He , Yunxiao Zou , Michael J. Mantor , Radhakrishna Giduthuri , Eric J. Finger , Brian D. Emberling
- Applicant: Advanced Micro Devices, Inc.
- Applicant Address: US CA Sunnyvale
- Assignee: Advanced micro devices, inc.
- Current Assignee: Advanced micro devices, inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Kowert, Hood, Munyon, Rankin & Goetzel, P.C.
- Agent Rory D. Rankin
- Main IPC: G06F9/30
- IPC: G06F9/30 ; G06F7/483 ; G06F7/57

Abstract:
Systems, apparatuses, and methods for efficiently processing arithmetic operations are disclosed. A computing system includes a processor capable of executing single precision mathematical instructions on data sizes of M bits and half precision mathematical instructions on data sizes of N bits, which is less than M bits. At least two source operands with M bits indicated by a received instruction are read from a register file. If the instruction is a packed math instruction, at least a first source operand with a size of N bits less than M bits is selected from either a high portion or a low portion of one of the at least two source operands read from the register file. The instruction includes fields storing bits, each bit indicating the high portion or the low portion of a given source operand associated with a register identifier specified elsewhere in the instruction.
Public/Granted literature
- US20190129718A1 PACKED 16 BITS INSTRUCTION PIPELINE Public/Granted day:2019-05-02
Information query