Invention Grant
- Patent Title: Dynamical switching between EPT and shadow page tables for runtime processor verification
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Application No.: US17343078Application Date: 2021-06-09
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Publication No.: US11886906B2Publication Date: 2024-01-30
- Inventor: Chuanxiao Dong , Yaozu Dong , Zhiyuan Lv , Zhi Wang
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Nicholson De Vos Webster & Elliott LLP
- Main IPC: G06F9/455
- IPC: G06F9/455 ; G06F9/48

Abstract:
Implementations disclosed describe a system and a method to execute a virtual machine on a processing device, receive a request to access a memory page identified by a guest virtual memory address (GVA) in an address space of the virtual machine, translate the GVA to a guest physical memory address (GPA) using a guest page table (GPT) comprising a GPT entry mapping the GVA to the GPA, translate the GPA to a host physical address (HPA) of the memory page, store, in a translation lookaside buffer (TLB), a TLB entry mapping the GVA to the HPA, modify the GPT entry to designate the memory page as accessed, detect an attempt by an application to modify the GPT entry; generate, in response to the attempt to modify the GPT entry, a page fault; and flush, in response to the page fault, the TLB entry.
Public/Granted literature
- US20210294636A1 DYNAMICAL SWITCHING BETWEEN EPT AND SHADOW PAGE TABLES FOR RUNTIME PROCESSOR VERIFICATION Public/Granted day:2021-09-23
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