Invention Grant
- Patent Title: Bond pad layout including floating conductive sections
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Application No.: US17405812Application Date: 2021-08-18
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Publication No.: US11887949B2Publication Date: 2024-01-30
- Inventor: Su-Chueh Lo , Jian-Syu Lin , Yi-Fan Chang
- Applicant: MACRONIX INTERNATIONAL CO., LTD.
- Applicant Address: TW Hsinchu
- Assignee: MACRONIX INTERNATIONAL CO., LTD.
- Current Assignee: MACRONIX INTERNATIONAL CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Haynes Beffel & Wolfeld LLP
- Agent Andrew L. Dunlap
- Main IPC: H01L23/00
- IPC: H01L23/00

Abstract:
Disclosed is a semiconductor device that has a first layer including conductive material, a bond wire coupled to an upper surface of the first layer, and a second layer including conductive material underneath the first layer. One or more interconnects couple the second layer to the first layer. In an example, the second layer has a plurality of discontinuous sections that includes (i) a connected section coupled to the one or more interconnects and (ii) one or more floating sections that are at least in part surrounded by the connected section, where the one or more floating sections are electrically floating and isolated from the connected section. The semiconductor device also includes an under-pad circuit on a substrate underneath the second layer, the under-pad circuit to transmit signals to one or more components external to the semiconductor device though the first layer.
Public/Granted literature
- US20230056520A1 BOND PAD LAYOUT INCLUDING FLOATING CONDUCTIVE SECTIONS Public/Granted day:2023-02-23
Information query
IPC分类: