公开(公告)号：US20240305298A1

公开(公告)日：2024-09-12

申请号：US18181983

申请日：2023-03-10

Applicant: Macronix International Co., Ltd.

Inventor： Yi-Fan Chang ,  Su-Chueh Lo ,  Jeng-Kuan Lin

IPC: H03K19/0185 ,  G06F3/06 ,  G11C7/10 ,  H03K3/037 ,  H03K19/00

CPC classification number: H03K19/018521 ,  G06F3/0604 ,  G06F3/0656 ,  G06F3/0679 ,  G11C7/10 ,  H03K3/037 ,  H03K19/0005

Abstract: Systems, methods, circuits, and devices for managing data transfers in semiconductor devices are provided. In one aspect, an integrated circuit includes: a first interface for receiving higher-speed-type data, a second interface for receiving lower-speed-type data, a first logic circuit coupled to the first interface, a second logic circuit coupled to the second interface, and a driving circuit separately coupled to the first logic circuit and the second logic circuit. The first data interface, the first logic circuit, and the driving circuit are arranged in series to form a first data path for transferring the higher-speed-type data with a first speed. The second data interface, the second logic circuit, and the driving circuit are arranged in series to form a second data path for transferring the lower-speed-type data with a second speed. The first speed is higher the second speed.

公开(公告)号：US12218665B2

公开(公告)日：2025-02-04

申请号：US18181983

申请日：2023-03-10

Applicant: Macronix International Co., Ltd.

Inventor： Yi-Fan Chang ,  Su-Chueh Lo ,  Jeng-Kuan Lin

IPC: G06F12/00 ,  G06F3/06 ,  G11C7/10 ,  H03K3/037 ,  H03K19/00 ,  H03K19/0185

Abstract: Systems, methods, circuits, and devices for managing data transfers in semiconductor devices are provided. In one aspect, an integrated circuit includes: a first interface for receiving higher-speed-type data, a second interface for receiving lower-speed-type data, a first logic circuit coupled to the first interface, a second logic circuit coupled to the second interface, and a driving circuit separately coupled to the first logic circuit and the second logic circuit. The first data interface, the first logic circuit, and the driving circuit are arranged in series to form a first data path for transferring the higher-speed-type data with a first speed. The second data interface, the second logic circuit, and the driving circuit are arranged in series to form a second data path for transferring the lower-speed-type data with a second speed. The first speed is higher the second speed.

公开(公告)号：US10891184B2

公开(公告)日：2021-01-12

申请号：US16419430

申请日：2019-05-22

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Ken-Hui Chen ,  Kuen-Long Chang ,  Yi-Fan Chang

IPC: G06F3/06 ,  G06F11/10

Abstract: An integrated circuit device can comprise addressable memory, and a receiver. Data integrity logic can be coupled to the input data path and configured to receive a data stream having a reference address, and a plurality of data chunks with data integrity codes. Also, the data integrity logic can include a configuration store to store configuration data for the data integrity checking. Also, the integrated circuit can include logic to parse the data chunks and the data integrity codes from the data stream, and logic to compute computed data integrity codes of data chunks in the received data stream, and compare the computed data integrity codes with received data integrity codes to test for data errors in the received data stream. The data integrity logic includes logic responsive to the configuration data that control the data integrity logic. In one aspect, the data integrity data indicates a floating boundary data integrity mode or a fixed boundary data integrity mode.

公开(公告)号：US09876493B2

公开(公告)日：2018-01-23

申请号：US14693565

申请日：2015-04-22

Applicant: MACRONIX International Co., Ltd.

Inventor： Yi-Fan Chang ,  Chun-Yi Lee ,  Ken-Hui Chen ,  Kuen-Long Chang ,  Chun-Hsiung Hung

IPC: G11C8/00 ,  H03K17/00 ,  G11C8/10

CPC classification number: H03K17/007 ,  G11C8/00 ,  G11C8/10 ,  H03K2217/0036

Abstract: A decode switch and a method for controlling a decode switch are provided. The decode switch includes a power source providing a first voltage, a source capacitance coupled to the power source, and a target capacitance coupled to the power source. The power source charges the source capacitance to the first voltage. The source capacitance is connected to the target capacitance and the source capacitance charges the target capacitance to a second voltage. The power source charges the target capacitance from the second voltage to the first voltage.

公开(公告)号：US20250119142A1

公开(公告)日：2025-04-10

申请号：US18988186

申请日：2024-12-19

Applicant: Macronix International Co., Ltd.

Inventor： Yi-Fan Chang ,  Su-Chueh Lo ,  Jeng-Kuan Lin

IPC: H03K19/0185 ,  G06F3/06 ,  G11C7/10 ,  H03K3/037 ,  H03K19/00

Abstract: Systems, methods, circuits, and devices for managing data transfers in semiconductor devices are provided. In one aspect, a method includes: selecting a first interface to receive higher-speed-type data at a first clock frequency; transferring the higher-speed-type data with a first speed along a first data path from the first interface through a first logic circuit to a driving circuit; outputting the higher-speed-type data by the driving circuit; selecting a second interface to receive lower-speed-type data at a second clock frequency that is same as the first clock frequency; transferring the lower-speed-type data with a second speed along a second data path from the second interface through a second logic circuit to the driving circuit, the first speed being higher than the second speed; and outputting the lower-speed-type data by the driving circuit.

公开(公告)号：US11887949B2

公开(公告)日：2024-01-30

申请号：US17405812

申请日：2021-08-18

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Su-Chueh Lo ,  Jian-Syu Lin ,  Yi-Fan Chang

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L2224/04042 ,  H01L2224/05011 ,  H01L2224/05013 ,  H01L2224/05014 ,  H01L2224/05016 ,  H01L2224/05082 ,  H01L2224/05088 ,  H01L2224/05095

Abstract: Disclosed is a semiconductor device that has a first layer including conductive material, a bond wire coupled to an upper surface of the first layer, and a second layer including conductive material underneath the first layer. One or more interconnects couple the second layer to the first layer. In an example, the second layer has a plurality of discontinuous sections that includes (i) a connected section coupled to the one or more interconnects and (ii) one or more floating sections that are at least in part surrounded by the connected section, where the one or more floating sections are electrically floating and isolated from the connected section. The semiconductor device also includes an under-pad circuit on a substrate underneath the second layer, the under-pad circuit to transmit signals to one or more components external to the semiconductor device though the first layer.

公开(公告)号：US09412425B2

公开(公告)日：2016-08-09

申请号：US14673530

申请日：2015-03-30

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yung-Feng Lin ,  Su-Chueh Lo ,  Tai-Feng Chen ,  Yi-Fan Chang

IPC: G11C7/00 ,  G11C7/08 ,  G11C7/06 ,  G11C7/10 ,  G11C7/12

CPC classification number: G11C7/08 ,  G11C7/06 ,  G11C7/1012 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/12

Abstract: A memory device includes a plurality of sense amplifiers coupled with an array of memory cells, a plurality of output data lines receiving outputs of corresponding sense amplifiers, and a plurality of precharge circuits configured to apply a precharge voltage on the output data lines. A controller provides control signals to the sense amplifiers and to the precharge circuits, including to cause the precharge circuits to precharge the output data lines before the sense amplifiers drive output data signals to the output data lines. The plurality of sense amplifiers includes banks of sense amplifiers, and each bank includes a sense amplifier having an output driving each output data line. The memory device includes data output multiplexers having inputs coupled to the output data lines, and the precharge circuits are coupled to the output data lines between outputs of the sense amplifiers and the data output multiplexers.

公开(公告)号：US20150206557A1

公开(公告)日：2015-07-23

申请号：US14673530

申请日：2015-03-30

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yung-Feng Lin ,  Su-Chueh Lo ,  Tai-Feng Chen ,  Yi-Fan Chang

IPC: G11C7/08 ,  G11C7/12 ,  G11C7/10

CPC classification number: G11C7/08 ,  G11C7/06 ,  G11C7/1012 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/12

Abstract: A memory device includes a plurality of sense amplifiers coupled with an array of memory cells, a plurality of output data lines receiving outputs of corresponding sense amplifiers, and a plurality of precharge circuits configured to apply a precharge voltage on the output data lines. A controller provides control signals to the sense amplifiers and to the precharge circuits, including to cause the precharge circuits to precharge the output data lines before the sense amplifiers drive output data signals to the output data lines. The plurality of sense amplifiers includes banks of sense amplifiers, and each bank includes a sense amplifier having an output driving each output data line. The memory device includes data output multiplexers having inputs coupled to the output data lines, and the precharge circuits are coupled to the output data lines between outputs of the sense amplifiers and the data output multiplexers.

Abstract translation: 存储器件包括与存储器单元阵列耦合的多个读出放大器，接收对应的读出放大器的输出的多个输出数据线以及被配置为在输出数据线上施加预充电电压的多个预充电电路。 控制器向读出放大器和预充电电路提供控制信号，包括在读出放大器将输出数据信号驱动到输出数据线之前使预充电电路对输出数据线进行预充电。 多个读出放大器包括读出放大器组，并且每个存储体包括具有驱动每个输出数据线的输出的读出放大器。 存储器件包括具有耦合到输出数据线的输入的数据输出多路复用器，并且预充电电路耦合到读出放大器和数据输出多路复用器的输出之间的输出数据线。

公开(公告)号：US09001604B2

公开(公告)日：2015-04-07

申请号：US13801500

申请日：2013-03-13

Applicant: Macronix International Co., Ltd.

Inventor： Yung-Feng Lin ,  Su-Chueh Lo ,  Tai-Feng Chen ,  Yi-Fan Chang

IPC: G11C7/00 ,  G11C7/06 ,  G11C7/08 ,  G11C7/10

CPC classification number: G11C7/08 ,  G11C7/06 ,  G11C7/1012 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/12

Abstract: A memory device includes a plurality of sense amplifiers coupled with an array of memory cells, a plurality of output data lines receiving outputs of corresponding sense amplifiers, and a plurality of precharge circuits configured to apply a precharge voltage on the output data lines. A controller provides control signals to the sense amplifiers and to the precharge circuits, including to cause the precharge circuits to precharge the output data lines before the sense amplifiers drive output data signals to the output data lines. The plurality of sense amplifiers includes banks of sense amplifiers, and each bank includes a sense amplifier having an output driving each output data line. The memory device includes data output multiplexers having inputs coupled to the output data lines, and the precharge circuits are coupled to the output data lines between outputs of the sense amplifiers and the data output multiplexers.

Abstract translation: 存储器件包括与存储器单元阵列耦合的多个读出放大器，接收对应的读出放大器的输出的多个输出数据线以及被配置为在输出数据线上施加预充电电压的多个预充电电路。 控制器向读出放大器和预充电电路提供控制信号，包括在读出放大器将输出数据信号驱动到输出数据线之前使预充电电路对输出数据线进行预充电。 多个读出放大器包括读出放大器组，并且每个存储体包括具有驱动每个输出数据线的输出的读出放大器。 存储器件包括具有耦合到输出数据线的输入的数据输出多路复用器，并且预充电电路耦合到读出放大器和数据输出多路复用器的输出之间的输出数据线。

公开(公告)号：US20140269125A1

公开(公告)日：2014-09-18

申请号：US13801500

申请日：2013-03-13

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yung-Feng Lin ,  Su-Chueh Lo ,  Tai-Feng Chen ,  Yi-Fan Chang

IPC: G11C7/06

CPC classification number: G11C7/08 ,  G11C7/06 ,  G11C7/1012 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/12

Abstract: A memory device includes a plurality of sense amplifiers coupled with an array of memory cells, a plurality of output data lines receiving outputs of corresponding sense amplifiers, and a plurality of precharge circuits configured to apply a precharge voltage on the output data lines. A controller provides control signals to the sense amplifiers and to the precharge circuits, including to cause the precharge circuits to precharge the output data lines before the sense amplifiers drive output data signals to the output data lines. The plurality of sense amplifiers includes banks of sense amplifiers, and each bank includes a sense amplifier having an output driving each output data line. The memory device includes data output multiplexers having inputs coupled to the output data lines, and the precharge circuits are coupled to the output data lines between outputs of the sense amplifiers and the data output multiplexers.

Abstract translation: 存储器件包括与存储器单元阵列耦合的多个读出放大器，接收对应的读出放大器的输出的多个输出数据线以及被配置为在输出数据线上施加预充电电压的多个预充电电路。 控制器向读出放大器和预充电电路提供控制信号，包括在读出放大器将输出数据信号驱动到输出数据线之前使预充电电路对输出数据线进行预充电。 多个读出放大器包括读出放大器组，并且每个存储体包括具有驱动每个输出数据线的输出的读出放大器。 存储器件包括具有耦合到输出数据线的输入的数据输出多路复用器，并且预充电电路耦合到读出放大器和数据输出多路复用器的输出之间的输出数据线。