Invention Grant
- Patent Title: Wafer-level test method for optoelectronic chips
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Application No.: US17770916Application Date: 2020-06-19
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Publication No.: US11906579B2Publication Date: 2024-02-20
- Inventor: Tobias Gnausch , Armin Grundmann , Thomas Kaden , Norik Janunts , Robert Buettner , Christian Karras
- Applicant: JENOPTIK Optical Systems GmbH
- Applicant Address: DE Jena
- Assignee: JENOPTIK GmbH
- Current Assignee: JENOPTIK GmbH
- Current Assignee Address: DE Jena
- Agency: Christensen, Fonder, Dardi & Herbert PLLC
- Priority: DE 2019007516.1 2019.10.25
- International Application: PCT/DE2020/100521 2020.06.19
- International Announcement: WO2021/078318A 2021.04.29
- Date entered country: 2022-04-21
- Main IPC: G01R31/28
- IPC: G01R31/28 ; G01R31/311

Abstract:
A method for the testing of optoelectronic chips which are arranged on a wafer and have electrical interfaces in the form of contact pads and optical interfaces which are arranged to be fixed relative thereto in the form of optical deflection elements, e.g., grating couplers, with a specific coupling angle. The wafer is adjusted in three adjustment steps with one of the chips relative to a contacting module such that the electrical interfaces of the chip and contacting module contact one another, and the optical interfaces of the chip and contacting module occupy a maximum position of the optical coupling.
Public/Granted literature
- US20220397602A1 WAFER-LEVEL TEST METHOD FOR OPTOELECTRONIC CHIPS Public/Granted day:2022-12-15
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