Invention Grant
- Patent Title: Bond enhancement structure in microelectronics for trapping contaminants during direct-bonding processes
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Application No.: US17681019Application Date: 2022-02-25
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Publication No.: US11967575B2Publication Date: 2024-04-23
- Inventor: Guilian Gao , Javier A. DeLaCruz , Shaowu Huang , Liang Wang , Gaius Gillman Fountain, Jr. , Rajesh Katkar , Cyprian Emeka Uzoh
- Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
- Applicant Address: US CA San Jose
- Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
- Current Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
- Current Assignee Address: US CA San Jose
- Agency: Knobbe, Martens, Olson & Bear, LLP
- Main IPC: H01L23/00
- IPC: H01L23/00

Abstract:
Structures and techniques provide bond enhancement in microelectronics by trapping contaminants and byproducts during bonding processes, and arresting cracks. Example bonding surfaces are provided with recesses, sinks, traps, or cavities to capture small particles and gaseous byproducts of bonding that would otherwise create detrimental voids between microscale surfaces being joined, and to arrest cracks. Such random voids would compromise bond integrity and electrical conductivity of interconnects being bonded. In example systems, a predesigned recess space or predesigned pattern of recesses placed in the bonding interface captures particles and gases, reducing the formation of random voids, thereby improving and protecting the bond as it forms. The recess space or pattern of recesses may be placed where particles collect on the bonding surface, through example methods of determining where mobilized particles move during bond wave propagation. A recess may be repeated in a stepped reticule pattern at the wafer level, for example, or placed by an aligner or alignment process.
Public/Granted literature
- US20220246564A1 BOND ENHANCEMENT STRUCTURE IN MICROELECTRONICS FOR TRAPPING CONTAMINANTS DURING DIRECT-BONDING PROCESSES Public/Granted day:2022-08-04
Information query
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