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公开(公告)号：US12100676B2
公开(公告)日：2024-09-24
申请号：US17559485
申请日：2021-12-22
IPC分类号： H01L23/00
CPC分类号： H01L24/08 , H01L24/80 , H01L2224/08057 , H01L2224/08147 , H01L2224/80895 , H01L2224/80896
摘要： Devices and techniques including process steps make use of recesses in conductive interconnect structures to form reliable low temperature metallic bonds. A fill layer is deposited into the recesses prior to bonding. First conductive interconnect structures are bonded at ambient temperatures to second metallic interconnect structures using direct bonding techniques, with the fill layers in the recesses in one or both of the first and second interconnect structures.
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公开(公告)号：US20240194625A1
公开(公告)日：2024-06-13
申请号：US18582312
申请日：2024-02-20
发明人： Guilian Gao , Bongsub Lee , Gaius Gillman Fountain, JR. , Cyprian Emeka Uzoh , Laura Wills Mirkarimi , Belgacem Haba , Rajesh Katkar
IPC分类号： H01L23/00 , H01L21/768 , H01L23/48 , H01L25/00 , H01L25/065
CPC分类号： H01L24/08 , H01L21/76898 , H01L23/481 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/09 , H01L24/80 , H01L25/0657 , H01L25/50 , H01L24/94 , H01L2224/05147 , H01L2224/05181 , H01L2224/05184 , H01L2224/08146 , H01L2224/80896
摘要： Representative techniques and devices including process steps may be employed to mitigate the potential for delamination of bonded microelectronic substrates due to metal expansion at a bonding interface. For example, a metal pad having a larger diameter or surface area (e.g., oversized for the application) may be used when a contact pad is positioned over a TSV in one or both substrates.
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公开(公告)号：US11860415B2
公开(公告)日：2024-01-02
申请号：US17507019
申请日：2021-10-21
发明人： Shaowu Huang , Javier A. Delacruz , Liang Wang , Guilian Gao
CPC分类号： G02B6/13 , G02B2006/12061 , G02B2006/12097
摘要： Integrated optical waveguides, direct-bonded waveguide interface joints, optical routing and interconnects are provided. An example optical interconnect joins first and second optical conduits. A first direct oxide bond at room temperature joins outer claddings of the two optical conduits and a second direct bond joins the inner light-transmitting cores of the two conduits at an annealing temperature. The two low-temperature bonds allow photonics to coexist in an integrated circuit or microelectronics package without conventional high-temperatures detrimental to microelectronics. Direct-bonded square, rectangular, polygonal, and noncircular optical interfaces provide better matching with rectangular waveguides and better performance. Direct oxide-bonding processes can be applied to create running waveguides, photonic wires, and optical routing in an integrated circuit package or in chip-to-chip optical communications without need for conventional optical couplers. An example wafer-level process fabricates running waveguides, optical routing, and direct-bonded optical interconnects for silicon photonics and optoelectronics packages when two wafers are joined.
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公开(公告)号：US11749645B2
公开(公告)日：2023-09-05
申请号：US16439360
申请日：2019-06-12
发明人： Guilian Gao , Bongsub Lee , Gaius Gillman Fountain, Jr. , Cyprian Emeka Uzoh , Belgacem Haba , Laura Wills Mirkarimi , Rajesh Katkar
IPC分类号： H01L25/065 , H01L21/768 , H01L23/48 , H01L23/482 , H01L23/522 , H01L23/00
CPC分类号： H01L25/0657 , H01L21/76843 , H01L21/76895 , H01L21/76898 , H01L23/481 , H01L23/4824 , H01L23/5226 , H01L24/09 , H01L24/32 , H01L24/80 , H01L24/83 , H01L2224/08145 , H01L2224/80895 , H01L2224/80896 , H01L2225/06524 , H01L2225/06544
摘要： Representative techniques and devices including process steps may be employed to mitigate the potential for delamination of bonded microelectronic substrates due to metal expansion at a bonding interface. For example, a through-silicon via (TSV) may be disposed through at least one of the microelectronic substrates. The TSV is exposed at the bonding interface of the substrate and functions as a contact surface for direct bonding.
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公开(公告)号：US20230207402A1
公开(公告)日：2023-06-29
申请号：US18146326
申请日：2022-12-23
CPC分类号： H01L23/04 , H01L21/486 , H01L21/52
摘要： A bonded structure comprises a frame element having a cavity formed through its thickness. The frame element is directly bonded to a first element at a first side and to a second element at a second side enclosing the cavity. The frame element may comprise a through substrate via (TSV). Redundant conductive contact pads may be formed in bonding layers for enhanced direct bonding quality and reliability.
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公开(公告)号：US20230125395A1
公开(公告)日：2023-04-27
申请号：US18050010
申请日：2022-10-26
摘要： A multi-die electronic apparatus is disclosed. The multi-die electronic apparatus can comprise a first die comprising first communication pads, the first die having a first device surface including first devices, and a first back surface opposite the first device surface. A second die can include second communication pads, the second die having a second device surface including second devices, and a second back surface opposite the first device surface. The first and second dies can be vertically stacked with the second back surface facing the first device surface. At least one of the first communication pads can communicate a non-noise signal capacitively with at least one of the second communication pads.
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公开(公告)号：US20240312953A1
公开(公告)日：2024-09-19
申请号：US18671851
申请日：2024-05-22
IPC分类号： H01L23/00
CPC分类号： H01L24/80 , H01L24/08 , H01L2224/08145 , H01L2224/80031 , H01L2224/80143 , H01L2224/80895 , H01L2224/80896
摘要： A method of direct hybrid bonding first and second semiconductor elements of differential thickness is disclosed. The method can include patterning a plurality of first contact features on the first semiconductor element. The method can include second a plurality of second contact features on the second semiconductor element corresponding to the first contact features for direct hybrid bonding. The method can include applying a lithographic magnification correction factor to one of the first patterning and second patterning without applying the lithographic magnification correction factor to the other of the first patterning and the second patterning. In various embodiments, a differential expansion compensation structure can be disposed on at least one of the first and the second semiconductor elements. The differential expansion compensation structure can be configured to compensate for differential expansion between the first and second semiconductor elements to reduce misalignment between at least the second and fourth contact features.
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公开(公告)号：US20240282747A1
公开(公告)日：2024-08-22
申请号：US18653243
申请日：2024-05-02
IPC分类号： H01L23/00 , H01L21/683 , H01L21/78
CPC分类号： H01L24/83 , H01L21/6836 , H01L21/78 , H01L24/03 , H01L24/08 , H01L24/09 , H01L24/32 , H01L24/33 , H01L24/98 , H01L2221/68327 , H01L2221/68368 , H01L2221/68381 , H01L2224/03002 , H01L2224/08145 , H01L2224/09181 , H01L2224/32145 , H01L2224/33181 , H01L2224/80895 , H01L2224/83009 , H01L2224/83896 , H01L2224/83948
摘要： Devices and techniques include process steps for preparing various microelectronic components for bonding, such as for direct bonding without adhesive. The processes include providing a first bonding surface on a first surface of the microelectronic components, bonding a handle to the prepared first bonding surface, and processing a second surface of the microelectronic components while the microelectronic components are gripped at the handle. In some embodiments, the processes include removing the handle from the first bonding surface, and directly bonding the microelectronic components at the first bonding surface to other microelectronic components.
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公开(公告)号：US20240249998A1
公开(公告)日：2024-07-25
申请号：US18394985
申请日：2023-12-22
发明人： Guilian Gao , Belgacem Haba , Laura Mirkarimi
IPC分类号： H01L23/46 , H01L23/00 , H01L23/053 , H01L23/38
CPC分类号： H01L23/46 , H01L23/053 , H01L23/38 , H01L24/08 , H01L2224/08245
摘要： In some implementations, a device package may include a package substrate, a package cover disposed on the package substrate, and an integrated cooling assembly disposed between the package substrate and the package cover. The integrated cooling assembly may include a semiconductor device and a cold plate having a first side attached to the semiconductor device and a second side opposite the first side. An adhesive layer may be disposed between the package cover and the second side of the cold plate, and one or more surfaces of second side of the cold plate may be spaced apart from the package cover to define a coolant channel therebetween. The adhesive layer may seal the package cover to the cold plate around a perimeter of the coolant channel.
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公开(公告)号：US11955445B2
公开(公告)日：2024-04-09
申请号：US17836840
申请日：2022-06-09
发明人： Guilian Gao , Bongsub Lee , Gaius Gillman Fountain, Jr. , Cyprian Emeka Uzoh , Laura Wills Mirkarimi , Belgacem Haba , Rajesh Katkar
IPC分类号： H01L23/00 , H01L21/768 , H01L23/48 , H01L25/00 , H01L25/065
CPC分类号： H01L24/08 , H01L21/76898 , H01L23/481 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/09 , H01L24/80 , H01L25/0657 , H01L25/50 , H01L24/94 , H01L2224/05147 , H01L2224/05181 , H01L2224/05184 , H01L2224/08146 , H01L2224/80896
摘要： Representative techniques and devices including process steps may be employed to mitigate the potential for delamination of bonded microelectronic substrates due to metal expansion at a bonding interface. For example, a metal pad having a larger diameter or surface area (e.g., oversized for the application) may be used when a contact pad is positioned over a TSV in one or both substrates.
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