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公开(公告)号：US20240332231A1
公开(公告)日：2024-10-03
申请号：US18194591
申请日：2023-03-31
发明人： Cyprian Emeka Uzoh
IPC分类号： H01L23/00 , H01L23/31 , H01L23/498 , H01L25/065
CPC分类号： H01L24/08 , H01L23/3135 , H01L23/49894 , H01L25/0652 , H01L24/80 , H01L2224/08146 , H01L2224/08225 , H01L2224/80895 , H01L2924/182
摘要： Direct bond interconnect in topographic packages and methods of making. The topographic packages include a first die hybrid bonded to a substrate, the first die located in a first device level. A second die located in a second device level above the first device, the second die hybrid bonded to the first die. The topographic packages also include a third die located in a third device level above the second die, the third die hybrid bonded to a top surface of the second device level.
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公开(公告)号：US12100676B2
公开(公告)日：2024-09-24
申请号：US17559485
申请日：2021-12-22
IPC分类号： H01L23/00
CPC分类号： H01L24/08 , H01L24/80 , H01L2224/08057 , H01L2224/08147 , H01L2224/80895 , H01L2224/80896
摘要： Devices and techniques including process steps make use of recesses in conductive interconnect structures to form reliable low temperature metallic bonds. A fill layer is deposited into the recesses prior to bonding. First conductive interconnect structures are bonded at ambient temperatures to second metallic interconnect structures using direct bonding techniques, with the fill layers in the recesses in one or both of the first and second interconnect structures.
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公开(公告)号：US20240243085A1
公开(公告)日：2024-07-18
申请号：US18517681
申请日：2023-11-22
发明人： Paul M. Enquist
IPC分类号： H01L23/00 , H01L21/50 , H01L25/00 , H01L25/065
CPC分类号： H01L24/09 , H01L21/50 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/80 , H01L24/89 , H01L25/0657 , H01L25/50 , H01L2224/0345 , H01L2224/03452 , H01L2224/03462 , H01L2224/036 , H01L2224/03616 , H01L2224/03825 , H01L2224/05005 , H01L2224/05007 , H01L2224/05026 , H01L2224/05078 , H01L2224/05082 , H01L2224/05124 , H01L2224/05147 , H01L2224/0556 , H01L2224/05561 , H01L2224/05562 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/05655 , H01L2224/05657 , H01L2224/05666 , H01L2224/05676 , H01L2224/05681 , H01L2224/05684 , H01L2224/05686 , H01L2224/08112 , H01L2224/08121 , H01L2224/08123 , H01L2224/08145 , H01L2224/08147 , H01L2224/80011 , H01L2224/80031 , H01L2224/80035 , H01L2224/80047 , H01L2224/80075 , H01L2224/80097 , H01L2224/80099 , H01L2224/8019 , H01L2224/80194 , H01L2224/80895 , H01L2224/80896 , H01L2224/80935 , H01L2224/80986 , H01L2225/06513
摘要： A method for forming a direct hybrid bond and a device resulting from a direct hybrid bond including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, capped by a conductive barrier, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads capped by a second conductive barrier, aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads capped by conductive barriers formed by contact bonding of the first non-metallic region to the second non-metallic region.
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公开(公告)号：US20240194625A1
公开(公告)日：2024-06-13
申请号：US18582312
申请日：2024-02-20
发明人： Guilian Gao , Bongsub Lee , Gaius Gillman Fountain, JR. , Cyprian Emeka Uzoh , Laura Wills Mirkarimi , Belgacem Haba , Rajesh Katkar
IPC分类号： H01L23/00 , H01L21/768 , H01L23/48 , H01L25/00 , H01L25/065
CPC分类号： H01L24/08 , H01L21/76898 , H01L23/481 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/09 , H01L24/80 , H01L25/0657 , H01L25/50 , H01L24/94 , H01L2224/05147 , H01L2224/05181 , H01L2224/05184 , H01L2224/08146 , H01L2224/80896
摘要： Representative techniques and devices including process steps may be employed to mitigate the potential for delamination of bonded microelectronic substrates due to metal expansion at a bonding interface. For example, a metal pad having a larger diameter or surface area (e.g., oversized for the application) may be used when a contact pad is positioned over a TSV in one or both substrates.
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公开(公告)号：US20240186269A1
公开(公告)日：2024-06-06
申请号：US18061383
申请日：2022-12-02
发明人： Belgacem Haba
IPC分类号： H01L23/00 , H01L23/552 , H01L25/065
CPC分类号： H01L23/573 , H01L23/552 , H01L24/08 , H01L24/16 , H01L24/32 , H01L24/73 , H01L24/80 , H01L25/0657 , H01L2224/0801 , H01L2224/08057 , H01L2224/08145 , H01L2224/16221 , H01L2224/32221 , H01L2224/73204 , H01L2224/80895 , H01L2224/80896 , H01L2225/06517 , H01L2225/06524 , H01L2225/06568 , H01L2924/1431 , H01L2924/1434
摘要： A bonded structure is disclosed. The bonded structure can comprise a semiconductor element comprising active circuitry and a security die electrically connected and directly bonded to a surface of the semiconductor element without an adhesive along a bonding interface. The security die can include a security core. The security core can contain an encryption logic and a memory. The security core can be configured to decrypt data to be transferred to the active circuitry and to encrypt signals from the active circuitry.
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公开(公告)号：US20240170406A1
公开(公告)日：2024-05-23
申请号：US18339137
申请日：2023-06-21
发明人： Belgacem Haba
IPC分类号： H01L23/538 , H01L23/00 , H01L25/065
CPC分类号： H01L23/5383 , H01L24/08 , H01L24/80 , H01L24/96 , H01L24/97 , H01L25/0652 , H01L25/0655 , H01L2224/08155 , H01L2224/80001
摘要： A bonded structure is disclosed. The bonded structure can include an interconnect structure that has a first side and a second side opposite the first side. The bonded structure can also include a first die that is mounted to the first side of the interconnect structure. The first die can be directly bonded to the interconnect structure without an intervening adhesive. The bonded structure can also include a second die that is mounted to the first side of the interconnect structure. The bonded structure can further include an element that is mounted to the second side of the interconnect structure. The first die and the second die are electrically connected by way of at least the interconnect structure and the element.
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公开(公告)号：US11955393B2
公开(公告)日：2024-04-09
申请号：US17315170
申请日：2021-05-07
发明人： Rajesh Katkar , Laura Wills Mirkarimi , Bongsub Lee , Gaius Gillman Fountain, Jr. , Cyprian Emeka Uzoh
IPC分类号： H01L23/10 , H01L21/768 , H01L23/00
CPC分类号： H01L23/10 , H01L21/76807 , H01L21/76816 , H01L24/08 , H01L2924/01029
摘要： A bonded structure is disclosed. The bonded structure includes a first element and a second element that is bonded to the first element along a bonding interface. The bonding interface has an elongate conductive interface feature and a nonconductive interface feature. The bonded structure also includes an integrated device that is coupled to or formed with the first element or the second element. The elongate conductive interface feature has a recess through a portion of a thickness of the elongate conductive interface feature. A portion of the nonconductive interface feature is disposed in the recess.
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公开(公告)号：US20240071915A1
公开(公告)日：2024-02-29
申请号：US18342515
申请日：2023-06-27
发明人： Cyprian Emeka UZOH
IPC分类号： H01L23/528 , H01L21/768
CPC分类号： H01L23/528 , H01L21/76898
摘要： Techniques are employed to mitigate the anchoring effects of cavity sidewall adhesion on an embedded conductive interconnect structure, and to allow a lower annealing temperature to be used to join opposing conductive interconnect structures. A vertical gap may be disposed between the conductive material of an embedded interconnect structure and the sidewall of the cavity to laterally unpin the conductive structure and allow uniaxial expansion of the conductive material. Additionally or alternatively, one or more vertical gaps may be disposed within the bonding layer, near the embedded interconnect structure to laterally unpin the conductive structure and allow uniaxial expansion of the conductive material.
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9.发明公开公开(公告)号：US20240055407A1
公开(公告)日：2024-02-15
申请号：US18366569
申请日：2023-08-07
发明人： Thomas Workman , Belgacem Haba
IPC分类号： H01L25/065 , H01L23/00 , G01R31/28 , H01L23/528
CPC分类号： H01L25/0657 , H01L24/08 , G01R31/2884 , H01L23/528 , H01L2224/08148 , H01L2924/1431
摘要： A bonded structure for debugging integrated circuit devices and a method for debugging integrated circuit devices is disclosed. The bonded structure may comprise a debugging element and an integrated circuit device. The debugging element may comprise a debugging circuitry. The debugging element may be bonded to an integrated circuit device. The debugging element may be configured to debug the integrated circuit device.
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10.发明授权公开(公告)号：US11860415B2
公开(公告)日：2024-01-02
申请号：US17507019
申请日：2021-10-21
发明人： Shaowu Huang , Javier A. Delacruz , Liang Wang , Guilian Gao
CPC分类号： G02B6/13 , G02B2006/12061 , G02B2006/12097
摘要： Integrated optical waveguides, direct-bonded waveguide interface joints, optical routing and interconnects are provided. An example optical interconnect joins first and second optical conduits. A first direct oxide bond at room temperature joins outer claddings of the two optical conduits and a second direct bond joins the inner light-transmitting cores of the two conduits at an annealing temperature. The two low-temperature bonds allow photonics to coexist in an integrated circuit or microelectronics package without conventional high-temperatures detrimental to microelectronics. Direct-bonded square, rectangular, polygonal, and noncircular optical interfaces provide better matching with rectangular waveguides and better performance. Direct oxide-bonding processes can be applied to create running waveguides, photonic wires, and optical routing in an integrated circuit package or in chip-to-chip optical communications without need for conventional optical couplers. An example wafer-level process fabricates running waveguides, optical routing, and direct-bonded optical interconnects for silicon photonics and optoelectronics packages when two wafers are joined.
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