Invention Grant
- Patent Title: Reduce well dopant loss in FinFETs through co-implantation
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Application No.: US17664930Application Date: 2022-05-25
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Publication No.: US11978634B2Publication Date: 2024-05-07
- Inventor: Sih-Jie Liu , Chun-Feng Nieh , Huicheng Chang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Slater Matsil, LLP
- Main IPC: H01L21/265
- IPC: H01L21/265 ; H01L21/266 ; H01L21/28 ; H01L21/8238 ; H01L27/092 ; H01L29/66 ; H01L29/78 ; H10B10/00

Abstract:
A method of forming a semiconductor device includes performing a first implantation process on a semiconductor substrate to form a deep p-well region, performing a second implantation process on the semiconductor substrate with a diffusion-retarding element to form a co-implantation region, and performing a third implantation process on the semiconductor substrate to form a shallow p-well region over the deep p-well region. The co-implantation region is spaced apart from a top surface of the semiconductor substrate by a portion of the shallow p-well region, and the dee p-well region and the shallow p-well region are joined with each other. An n-type Fin Field-Effect Transistor (FinFET) is formed, with the deep p-well region and the shallow p-well region acting as a well region of the n-type FinFET.
Public/Granted literature
- US20220301874A1 Reduce Well Dopant Loss in FinFETs Through Co-Implantation Public/Granted day:2022-09-22
Information query
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