Invention Grant
- Patent Title: Processing pipeline with zero loop overhead
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Application No.: US17131970Application Date: 2020-12-23
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Publication No.: US11989554B2Publication Date: 2024-05-21
- Inventor: Kameran Azadet , Jeroen Leijten , Joseph Williams
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Banner & Witcoff Ltd.
- Main IPC: G06F9/38
- IPC: G06F9/38 ; G06F9/30 ; G06F9/46 ; G06F9/54

Abstract:
Techniques are disclosed for reducing or eliminating loop overhead caused by function calls in processors that form part of a pipeline architecture. The processors in the pipeline process data blocks in an iterative fashion, with each processor in the pipeline completing one of several iterations associated with a processing loop for a commonly-executed function. The described techniques leverage the use of message passing for pipelined processors to enable an upstream processor to signal to a downstream processor when processing has been completed, and thus a data block is ready for further processing in accordance with the next loop processing iteration. The described techniques facilitate a zero loop overhead architecture, enable continuous data block processing, and allow the processing pipeline to function indefinitely within the main body of the processing loop associated with the commonly-executed function where efficiency is greatest.
Public/Granted literature
- US20220197641A1 PROCESSING PIPELINE WITH ZERO LOOP OVERHEAD Public/Granted day:2022-06-23
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