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    CREST FACTOR REDUCTION CANCELLATION PULSE HAVING A REDUCED LENGTH
    2.
    发明公开
    CREST FACTOR REDUCTION CANCELLATION PULSE HAVING A REDUCED LENGTH 审中-公开

    公开(公告)号：US20240007337A1

    公开(公告)日：2024-01-04

    申请号：US17854155

    申请日：2022-06-30

    Applicant: Intel Corporation

    Inventor： Sunitha Motipalli ,  Kameran Azadet ,  Albert Molina ,  Joseph Othmer ,  Kannan Rajamani

    IPC: H04L27/26

    CPC classification number: H04L27/2618 ,  H04L27/262 ,  H04L27/2615 ,  H04B1/0475

    Abstract: Techniques are disclosed for the use of Crest Factor Reduction (CFR) technique that utilizes a cancellation pulse signal having a reduced length. The CFR technique may be applied to a signal to be transmitted, which may comprise a composite signal having one or more carrier signals. Each carrier signal of the composite signal may be filtered via a respective channel filter and then recombined to form the signal to be transmitted, on which the CFR operations are then applied. The length of the cancellation pulse signal is less than the number of taps of the channel filter with the largest number of taps. This reduction in cancellation pulse signal length significantly reduces the processing power required to perform the CFR operations while maintaining regulatory emissions compliance.

    VECTOR PROCESSOR SUPPORTING LINEAR INTERPOLATION ON MULTIPLE DIMENSIONS
    5.
    发明申请
    VECTOR PROCESSOR SUPPORTING LINEAR INTERPOLATION ON MULTIPLE DIMENSIONS 有权

    公开(公告)号：US20220197640A1

    公开(公告)日：2022-06-23

    申请号：US17131939

    申请日：2020-12-23

    Applicant: Intel Corporation

    Inventor： Kameran Azadet ,  Joseph Williams ,  Zoran Zivkovic

    IPC: G06F9/30 ,  G06F9/38 ,  G06F16/901

    Abstract: Techniques are disclosed for a vector processor architecture that enables data interpolation in accordance with multiple dimensions, such as one-, two-, and three-dimensional linear interpolation. The vector processor architecture includes a vector processor and accompanying vector addressable memory that enable a simultaneous retrieval of multiple entries in the vector addressable memory to facilitate linear interpolation calculations. The vector processor architecture vastly increases the speed in which such calculations may occur compared to conventional processing architectures. Example implementations include the calculation of digital pre-distortion (DPD) coefficients for use with radio frequency (RF) transmitter chains to support multi-band applications.

    Apparatus for generating a plurality of phase-shifted clock signals, electronic system, base station and mobile device
    6.
    发明授权
    Apparatus for generating a plurality of phase-shifted clock signals, electronic system, base station and mobile device 有权

    公开(公告)号：US11183993B2

    公开(公告)日：2021-11-23

    申请号：US16724564

    申请日：2019-12-23

    Applicant: Intel Corporation

    Inventor： Hundo Shin ,  Kameran Azadet ,  Martin Clara ,  Daniel Gruber

    IPC: H03H11/16 ,  H03K5/13 ,  H03K5/00 ,  H04W88/02 ,  H04W88/08

    Abstract: An apparatus for generating a plurality of phase-shifted clock signals is provided. The apparatus comprises a first input node configured to receive a first reference clock signal. Further, the apparatus comprises a second input node configured to receive a second reference clock signal. The apparatus comprises a plurality of output nodes each configured to output one of the plurality of phase-shifted clock signals. Additionally, the apparatus comprises a cascade of coupled clock generation circuits configured to generate the plurality of phase-shifted clock signals based on the first reference clock signal and the second reference clock signal. Input nodes of the first clock generation circuit of the cascade of clock generation circuits are coupled to the first input node and the second input node. Output nodes of the last clock generation circuit of the cascade of clock generation circuits are coupled to the plurality of output nodes. At least one of the plurality of clock generation circuits is an active circuit, and at least one of the plurality of clock generation circuits is a passive circuit.

    n-Bit successive approximation register analog-to-digital converter and method for calibrating the same, receiver, base station and mobile device
    7.
    发明授权
    n-Bit successive approximation register analog-to-digital converter and method for calibrating the same, receiver, base station and mobile device 有权

    公开(公告)号：US11177820B2

    公开(公告)日：2021-11-16

    申请号：US16933292

    申请日：2020-07-20

    Applicant: Intel Corporation

    Inventor： Albert Molina ,  Martin Clara ,  Matteo Camponeschi ,  Christian Lindholm ,  Kameran Azadet

    IPC: H03M1/10 ,  H04B1/16

    Abstract: A n-bit Successive Approximation Register Analog-to-Digital Converter, SAR ADC, is provided. The SAR ADC comprises a respective plurality of sampling cells for each bit of the n-bit of the SAR ADC. Each sampling cell comprises a capacitive element coupled to a cell output of the sampling cell in order to provide a cell output signal. Further, each sampling cell comprises a first cell input for receiving a first signal, and a first switch circuit capable of selectively coupling the first cell input to the capacitive element. Each cell additionally comprises a second cell input for receiving a second signal, and a third cell input for receiving a third signal. The third signal exhibits opposite polarity compared to the second signal. Each sampling cell comprises a second switch circuit capable of selectively coupling one of the second cell input and the third cell input to the capacitive element. The SAR ADC further comprises at least one comparator circuit coupled to the sampling cells. The at least one comparator circuit is configured to output a comparison signal based on the cell output signals of the sampling cells. Additionally, the SAR ADC comprises a calibration circuit configured to supply at least one respective control signal to the respective second switch circuit of the sampling cells for controlling the second switch circuits.

    ANALOG-TO-DIGITAL CONVERTER SYSTEM, TRANSCEIVER, BASE STATION AND MOBILE DEVICE
    8.
    发明申请
    ANALOG-TO-DIGITAL CONVERTER SYSTEM, TRANSCEIVER, BASE STATION AND MOBILE DEVICE 有权

    公开(公告)号：US20210194747A1

    公开(公告)日：2021-06-24

    申请号：US16724458

    申请日：2019-12-23

    Applicant: Intel Corporation

    Inventor： Kameran Azadet ,  Martin Clara ,  Daniel Gruber ,  Christian Lindholm ,  Hundo Shin

    IPC: H04L27/36 ,  H03M1/10 ,  H03M1/06

    Abstract: An Analog-to-Digital Converter, ADC, system is provided. The ADC system comprises a plurality of ADC circuits and a first input for receiving a transmit signal of a transceiver. One ADC circuit of the plurality of ADC circuits is coupled to the first input and configured to provide first digital data based on the transmit signal. The ADC system further comprises a second input for receiving a receive signal of the transceiver. The other ADC circuits of the plurality of ADC circuits are coupled to the second input, wherein the other ADC circuits of the plurality of ADC circuits are time-interleaved and configured to provide second digital data based on the receive signal. Additionally, the ADC system comprises a first output configured to output digital feedback data based on the first digital data, and a second output configured to output digital receive data based on the second digital data.

    n-bit successive approximation register analog-to-digital converter and method for calibrating the same, receiver, base station and mobile device
    9.
    发明授权
    n-bit successive approximation register analog-to-digital converter and method for calibrating the same, receiver, base station and mobile device 有权

    公开(公告)号：US10742225B1

    公开(公告)日：2020-08-11

    申请号：US16728226

    申请日：2019-12-27

    Applicant: Intel Corporation

    Inventor： Albert Molina ,  Martin Clara ,  Matteo Camponeschi ,  Christian Lindholm ,  Kameran Azadet

    IPC: H03M1/10 ,  H04B1/16

    Abstract: A n-bit Successive Approximation Register Analog-to-Digital Converter, SAR ADC, is provided. The SAR ADC comprises a respective plurality of sampling cells for each bit of the n-bit of the SAR ADC. Each sampling cell comprises a capacitive element coupled to a cell output of the sampling cell in order to provide a cell output signal. Further, each sampling cell comprises a first cell input for receiving a first signal, and a first switch circuit capable of selectively coupling the first cell input to the capacitive element. Each cell additionally comprises a second cell input for receiving a second signal, and a third cell input for receiving a third signal. The third signal exhibits opposite polarity compared to the second signal. Each sampling cell comprises a second switch circuit capable of selectively coupling one of the second cell input and the third cell input to the capacitive element. The SAR ADC further comprises at least one comparator circuit coupled to the sampling cells. The at least one comparator circuit is configured to output a comparison signal based on the cell output signals of the sampling cells. Additionally, the SAR ADC comprises a calibration circuit configured to supply at least one respective control signal to the respective second switch circuit of the sampling cells for controlling the second switch circuits.

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