Invention Grant
- Patent Title: Adaptive optimization of error-handling flows in memory devices
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Application No.: US17884327Application Date: 2022-08-09
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Publication No.: US12019874B2Publication Date: 2024-06-25
- Inventor: Jay Sarkar , Vamsi Pavan Rayaprolu , Ipsita Ghosh
- Applicant: MICRON TECHNOLOGY, INC.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Lowenstein Sandler LLP
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F3/06

Abstract:
Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including applying an ordered set of error-handling operations to be performed on data residing in a segment of the memory device as an input to a trained machine learning model, wherein the trained machine learning model is based on latency data for previously-performed error-handling operations; and obtaining an output of the trained machine learning model, the output comprising a reordered set of error-handling operations to be performed on the data residing in the segment of the memory device, and wherein the reordered set adjusts an order of one or more error-handling operations of the ordered set of error-handling operations.
Public/Granted literature
- US20240053893A1 ADAPTIVE OPTIMIZATION OF ERROR-HANDLING FLOWS IN MEMORY DEVICES Public/Granted day:2024-02-15
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