公开(公告)号：US20240070008A1

公开(公告)日：2024-02-29

申请号：US17897910

申请日：2022-08-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jay Sarkar ,  Ipsita Ghosh ,  Vamsi Pavan Rayaprolu

IPC: G06F11/07

CPC classification number: G06F11/0784 ,  G06F11/0757 ,  G06F11/0787

Abstract: Systems and methods are disclosed including a memory and a processing device operatively coupled to the memory. The processing device can perform operations including receiving log data related to a first order of a set of error-handling operations performed on data residing in a segment of a memory device; applying an optimization model to the log data, wherein the optimization model is based on probability data of error recovery and latency data of the set of error-handling operations; and responsive to applying the optimization model to the log data, obtaining, as an output of the optimization model, a second order of the set of error-handling operations, wherein the second order adjusts an order of one or more error-handling operations of the set of error-handling operations in the first order.

公开(公告)号：US20240256375A1

公开(公告)日：2024-08-01

申请号：US18631928

申请日：2024-04-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jay Sarkar ,  Ipsita Ghosh ,  Vamsi Pavan Rayaprolu

IPC: G06F11/07

CPC classification number: G06F11/0784 ,  G06F11/0757 ,  G06F11/0787

Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including selecting sample data residing in the memory device; running a test on the sample data regarding a set of error-handling operations; and generating log data comprising a first order of the set of error-handling operations to be performed on data residing in a segment of the memory device.

公开(公告)号：US12019874B2

公开(公告)日：2024-06-25

申请号：US17884327

申请日：2022-08-09

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jay Sarkar ,  Vamsi Pavan Rayaprolu ,  Ipsita Ghosh

IPC: G06F12/00 ,  G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0629 ,  G06F3/0679

Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including applying an ordered set of error-handling operations to be performed on data residing in a segment of the memory device as an input to a trained machine learning model, wherein the trained machine learning model is based on latency data for previously-performed error-handling operations; and obtaining an output of the trained machine learning model, the output comprising a reordered set of error-handling operations to be performed on the data residing in the segment of the memory device, and wherein the reordered set adjusts an order of one or more error-handling operations of the ordered set of error-handling operations.

公开(公告)号：US20240302968A1

公开(公告)日：2024-09-12

申请号：US18666667

申请日：2024-05-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jay Sarkar ,  Vamsi Pavan Rayaprolu ,  Ipsita Ghosh

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0629 ,  G06F3/0679

Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including sending, to a device that provides error-handling flow optimization, an ordered set of error-handling operations to be performed to recover data residing in a segment of the memory device; receiving, from the device that provides the error-handling flow optimization, a reordered set of error-handling operations, wherein the reordered set adjusts an order of one or more error-handling operations of the ordered set of error-handling operations, wherein the reordered set is obtained by applying the ordered set of error-handling operations to a trained machine learning model, wherein the trained machine learning model is based on latency data for previously-performed error-handling operations, and wherein the latency data for the previously-performed error-handling operations depends on a workload of the segment of the memory device; and performing one or more error-handling operations of the reordered set of error-handling operations to the data residing in the segment of the memory device.

公开(公告)号：US11994936B2

公开(公告)日：2024-05-28

申请号：US17897910

申请日：2022-08-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jay Sarkar ,  Ipsita Ghosh ,  Vamsi Pavan Rayaprolu

IPC: G06F11/07

CPC classification number: G06F11/0784 ,  G06F11/0757 ,  G06F11/0787

Abstract: Systems and methods are disclosed including a memory and a processing device operatively coupled to the memory. The processing device can perform operations including receiving log data related to a first order of a set of error-handling operations performed on data residing in a segment of a memory device; applying an optimization model to the log data, wherein the optimization model is based on probability data of error recovery and latency data of the set of error-handling operations; and responsive to applying the optimization model to the log data, obtaining, as an output of the optimization model, a second order of the set of error-handling operations, wherein the second order adjusts an order of one or more error-handling operations of the set of error-handling operations in the first order.

公开(公告)号：US20240053893A1

公开(公告)日：2024-02-15

申请号：US17884327

申请日：2022-08-09

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jay Sarkar ,  Vamsi Pavan Rayaprolu ,  Ipsita Ghosh

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0679 ,  G06F3/0629

Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including applying an ordered set of error-handling operations to be performed on data residing in a segment of the memory device as an input to a trained machine learning model, wherein the trained machine learning model is based on latency data for previously-performed error-handling operations; and obtaining an output of the trained machine learning model, the output comprising a reordered set of error-handling operations to be performed on the data residing in the segment of the memory device, and wherein the reordered set adjusts an order of one or more error-handling operations of the ordered set of error-handling operations.