Invention Grant
- Patent Title: Systems and methods for fabricating silicon die stacks for electron emitter array chips
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Application No.: US18282005Application Date: 2022-03-14
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Publication No.: US12027489B2Publication Date: 2024-07-02
- Inventor: Ukyo Jeong , Ghiyuun Kang
- Applicant: NANO-X IMAGING LTD
- Applicant Address: IL Neve-Ilan
- Assignee: NANO-X IMAGING LTD
- Current Assignee: NANO-X IMAGING LTD
- Current Assignee Address: IL Neve-Ilan
- Agency: AlphaPatent Associates Ltd.
- Agent Daniel J. Swirsky
- International Application: PCT/IB2022/052288 2022.03.14
- International Announcement: WO2022/195457A 2022.09.22
- Date entered country: 2023-09-14
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01J9/02 ; H01J35/06

Abstract:
A method for fabricating silicon die stacks for electron emitter chips by applying sintering to bind a silicon substrate die to other die layers. Metal powder is applied to the bonding surface of the die, covered with the chip carrier or chip and compressed between two heated plates. The bonding pads of the die may be conductively coupled to corresponding bonding pads of the other die layers.
Public/Granted literature
- US20240047415A1 SYSTEMS AND METHODS FOR FABRICATING SILICON DIE STACKS FOR ELECTRON EMITTER ARRAY CHIPS Public/Granted day:2024-02-08
Information query
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