发明授权
- 专利标题: Management of error-handling flows in memory devices using probability data structure
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申请号: US17943082申请日: 2022-09-12
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公开(公告)号: US12032833B2公开(公告)日: 2024-07-09
- 发明人: Aswin Thiruvengadam , Vamsi Pavan Rayaprolu
- 申请人: MICRON TECHNOLOGY, INC.
- 申请人地址: US ID Boise
- 专利权人: MICRON TECHNOLOGY, INC.
- 当前专利权人: MICRON TECHNOLOGY, INC.
- 当前专利权人地址: US ID Boise
- 代理机构: Lowenstein Sandler LLP
- 主分类号: G06F3/06
- IPC分类号: G06F3/06
摘要:
Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including running sample data through each of a set of error-handling operations performed on data residing in a segment of the memory device in an existing order associated with a workload; obtaining error recovery data as a result of running the sample data; and determining an optimized order of the set of error-handling operations based on probability of error recovery and latency data, wherein the probability of error recovery is based on the error recovery data, and wherein the optimized order comprises an adjustment to an order of one or more error-handling operations of the set of error-handling operations in the existing order.
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