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公开(公告)号：US20240289032A1
公开(公告)日：2024-08-29
申请号：US18659217
申请日：2024-05-09
IPC分类号： G06F3/06
CPC分类号： G06F3/0619 , G06F3/0655 , G06F3/0679
摘要： Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including running sample data through each of a set of error-handling operations performed on data residing in a segment of the memory device in an existing order; and determining an optimized order of the set of error-handling operations based on probability data and latency data, wherein the probability data is associated with a result of running the sample data, and wherein the optimized order comprises an adjustment to an order of one or more error-handling operations of the set of error-handling operations in the existing order.
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公开(公告)号：US11493550B2
公开(公告)日：2022-11-08
申请号：US16711106
申请日：2019-12-11
摘要： A thermal chamber includes multiple sides, such as a back side, a front side, a first end, a second end, a top side, and a bottom side. An electronic circuit board is adjustably mounted to the bottom side and positioned above the bottom side of the thermal chamber. In the closed position the multiple sides form an enclosed chamber. The top side includes one or more ports orientated along the horizontal axis. Each of the one or more ports includes a top side open area that exposes the enclosed chamber. Each of the one or more ports is configured to receive a temperature control component that transfers thermal energy locally to and from multiple electronic devices of an electronic system that is coupled to and positioned above the electronic circuit board.
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公开(公告)号：US11131705B2
公开(公告)日：2021-09-28
申请号：US16209393
申请日：2018-12-04
摘要： A request to perform a test with one or more memory components can be received. Available test resources of a test platform that is associated with memory components can be determined. The desired characteristics of the one or more memory components that are specified by the test can be determined. One or more of the available test resources of the test platform to the test can be assigned based on characteristics of respective memory components associated with the one or more of the available test resources and the desired characteristics of the one or more memory components of the test. Furthermore, the test can be performed with the assigned one or more of the available test resources of the test platform.
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公开(公告)号：US11121125B2
公开(公告)日：2021-09-14
申请号：US16218038
申请日：2018-12-12
摘要： A thermal chamber includes multiple sides, such as a back side, a front side, a first end, a second end, a top side, and a bottom side. The multiple sides form a cavity. The top side includes one or more ports. Each of the one or more ports includes a top side open area that exposes the cavity within the thermal chamber. Each of the one or more ports is configured to receive a temperature control component that transfers thermal energy to and from an electrical device exposed via the cavity. The top side open area of the one or more ports has a corresponding bottom side open area of the bottom side located below the top side open area. The bottom side open area is configured to allow the temperature control component to contact the electrical device that is exposed via the bottom side open area.
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公开(公告)号：US11043269B2
公开(公告)日：2021-06-22
申请号：US16889774
申请日：2020-06-01
摘要： Test resources of a test platform that are performing a test of memory components are determined. An indication that a particular test resource of the test resources of the test platform has failed can be received. The particular test resource is failed while performing a portion of the test of memory components. A remaining portion of the test of memory components can be performed based on the indication that the particular test resource of the test platform has failed.
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公开(公告)号：US20200294587A1
公开(公告)日：2020-09-17
申请号：US16889774
申请日：2020-06-01
摘要： Test resources of a test platform that are performing a test of memory components are determined. An indication that a particular test resource of the test resources of the test platform has failed can be received. The particular test resource is failed while performing a portion of the test of memory components. A remaining portion of the test of memory components can be performed based on the indication that the particular test resource of the test platform has failed.
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公开(公告)号：US20190303290A1
公开(公告)日：2019-10-03
申请号：US16442792
申请日：2019-06-17
IPC分类号： G06F12/02 , G06F13/16 , G11C16/32 , G11C16/34 , G11C16/20 , G11C11/406 , G11C29/02 , G06F16/18 , G11C7/20
摘要： The present disclosure includes apparatuses and methods related to determining trim settings on a memory device. An example apparatus can determine a set of trim settings for the array of memory cells based on the operational characteristics of the array of memory cells, wherein the set of trim settings are associated with desired operational characteristics for the array of memory cells.
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公开(公告)号：US10324839B2
公开(公告)日：2019-06-18
申请号：US15802652
申请日：2017-11-03
IPC分类号： G11C11/40 , G06F12/02 , G11C11/406 , G11C16/20 , G11C16/34 , G06F13/16 , G11C16/32 , G06F16/18
摘要： The present disclosure includes apparatuses and methods related to determining trim settings on a memory device. An example apparatus can determine a set of trim settings for the array of memory cells based on the operational characteristics of the array of memory cells, wherein the set of trim settings are associated with desired operational characteristics for the array of memory cells.
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公开(公告)号：US20190139619A1
公开(公告)日：2019-05-09
申请号：US15802597
申请日：2017-11-03
摘要： The present disclosure includes apparatuses and methods related to a memory system including a controller and an array of memory cells. An example apparatus can include a controller configured to receive operational characteristics of an array of memory cells based on prior operations performed by the array of memory cells, determine a set of trim settings for the array of memory cells based on the operational characteristics of the array of memory cells, wherein the set of trim settings are associated with desired operational characteristics for the array of memory cells, and send the set of trim settings to the array of memory cells.
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公开(公告)号：US20140245107A1
公开(公告)日：2014-08-28
申请号：US13779381
申请日：2013-02-27
发明人： Aswin Thiruvengadam , Angelo Visconti , Mauro Bonanomi , Richard E. Fackenthal , William Melton
IPC分类号： G06F11/16
CPC分类号： G06F11/1008 , G06F3/0619 , G06F3/064 , G06F3/0644 , G06F3/0673 , G06F3/0679 , G06F11/0751 , G06F11/1048 , G06F11/1666 , G11C7/1006 , G11C7/1012 , G11C13/0004 , G11C13/0069 , G11C16/10 , G11C19/00
摘要： This disclosure relates to avoiding a hard error in memory during write time by shifting data to be programmed to memory to mask the hard error. In one implementation, a method of programming data to a memory array includes obtaining error data corresponding to a selected memory cell, shifting a data pattern such that a value to be stored by the selected memory cell matches a value associated with a hard error, and programming the shifted data pattern to memory array such that the value programmed to the selected memory cell matches the value associated with the hard error.
摘要翻译： 本公开涉及通过将要编程的数据移动到存储器以避免硬错误而避免在写入时间期间的存储器中的硬错误。 在一个实现中，将数据编程到存储器阵列的方法包括获得与所选择的存储器单元相对应的错误数据，移位数据模式，使得所选存储器单元要存储的值与硬错误相关联的值匹配，以及 将移位的数据模式编程到存储器阵列，使得编程到所选择的存储器单元的值与与硬错误相关联的值匹配。
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