Invention Grant
- Patent Title: Static random access memory supporting a single clock cycle read-modify-write operation
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Application No.: US17861384Application Date: 2022-07-11
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Publication No.: US12040013B2Publication Date: 2024-07-16
- Inventor: Praveen Kumar Verma , Harsh Rawat
- Applicant: STMicroelectronics International N.V.
- Applicant Address: CH Geneva
- Assignee: STMicroelectronics International N.V.
- Current Assignee: STMicroelectronics International N.V.
- Current Assignee Address: CH Geneva
- Agency: Crowe & Dunlevy LLC
- Main IPC: G11C11/419
- IPC: G11C11/419 ; G11C11/418

Abstract:
A memory array includes memory cells forming a data word location accessed in response to a word line signal. A data sensing circuit configured to sense data on bit lines associated with the memory cells. The sensed data corresponds to a current data word stored at the data word location. A data latching circuit latches the sensed data for the current data word from the data sensing circuit. A data modification circuit then performs a mathematical modify operation on the current data word to generate a modified data word. The modified data word is then applied by a data writing circuit to the bit lines for writing back to the memory cells of the memory array at the data word location. The operations are advantageously performed within a single clock cycle.
Public/Granted literature
- US20230050783A1 STATIC RANDOM ACCESS MEMORY SUPPORTING A SINGLE CLOCK CYCLE READ-MODIFY-WRITE OPERATION Public/Granted day:2023-02-16
Information query
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