公开(公告)号：US11984151B2

公开(公告)日：2024-05-14

申请号：US17850207

申请日：2022-06-27

Applicant: STMicroelectronics International N.V.

Inventor： Harsh Rawat ,  Kedar Janardan Dhori ,  Promod Kumar ,  Nitin Chawla ,  Manuj Ayodhyawasi

IPC: G11C11/10 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4096

CPC classification number: G11C11/4085 ,  G11C11/4074 ,  G11C11/4094 ,  G11C11/4096

Abstract: A circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates, through a word line driver circuit for each row, word lines in parallel for an in-memory compute operation. A column processing circuit processes analog voltages developed on the bit lines in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A bit line precharge circuit generates a precharge voltage for application to each pair of bit lines. The precharge voltage has a first voltage level (not greater than a positive supply voltage for the SRAM cells) when the memory array is operating in a data read/write mode. The precharge voltage has a second voltage level (greater than the first voltage level) in advance of the simultaneous actuation of the word lines for the in-memory compute operation.

公开(公告)号：US20180166128A1

公开(公告)日：2018-06-14

申请号：US15375987

申请日：2016-12-12

Applicant: STMicroelectronics International N.V.

Inventor： Harsh Rawat ,  Abhishek Pathak

IPC: G11C11/419 ,  G11C11/418 ,  G06F1/06 ,  G06F13/16

CPC classification number: G11C11/419 ,  G06F1/06 ,  G06F13/1689 ,  G11C7/1075 ,  G11C8/16 ,  G11C11/413 ,  G11C11/418

Abstract: A memory array has word lines and bit lines. A row decoder is operable to decode a row address and select a corresponding word line. A read-write clock generator is operable to generate a hold clock signal. An address clock generator receives a read address, a write address, a dual port mode control signal, a read chip select signal, and a write chip select signal. When operating in dual port mode, and when operating in a read mode, the address clock generator applies a read delay to the read address and outputs the read address, as delayed, to the row pre-decoder as the address in response to the hold clock signal.

公开(公告)号：US12176025B2

公开(公告)日：2024-12-24

申请号：US17844955

申请日：2022-06-21

Applicant: STMicroelectronics International N.V.

Inventor： Harsh Rawat ,  Kedar Janardan Dhori ,  Promod Kumar ,  Nitin Chawla ,  Manuj Ayodhyawasi

IPC: G11C11/412 ,  G11C11/418 ,  G11C11/419

Abstract: An in-memory computation circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. Body bias nodes of the transistors in each SRAM cell are biased by a modulated body bias voltage. A row controller circuit simultaneously actuates word lines in parallel for an in-memory compute operation. A column processing circuit processes analog voltages developed on the bit lines in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A voltage generator circuit switches the modulated body bias voltage from a non-negative voltage level to a negative voltage level during the simultaneous actuation. The negative voltage level is adjusted dependent on integrated circuit process and/or temperature conditions in order to optimize protection against unwanted memory cell data flip.

公开(公告)号：US12068026B2

公开(公告)日：2024-08-20

申请号：US17852677

申请日：2022-06-29

Applicant: STMicroelectronics International N.V.

Inventor： Harsh Rawat ,  Praveen Kumar Verma

IPC: G11C11/419 ,  G11C11/412

CPC classification number: G11C11/419 ,  G11C11/412

Abstract: A method of memory reset includes precharging bit lines of a memory array, asserting a signal at a reset node to remove the precharge voltage, and selecting write drivers associated with the bit lines associated with columns of the memory array that contain memory cells to be reset, with the assertion of the signal at the reset node also resulting in application of desired logic states to inputs of the selected write drivers to cause those selected write drivers to change a logic state of the bit lines associated with those write drivers. The method continues with asserting each word line associated with a row of the memory that contains memory cells to be reset to write desired logic states to all of the memory cells of the columns and rows of the memory to be reset during a single clock cycle, and then deasserting those word lines.

公开(公告)号：US09786364B1

公开(公告)日：2017-10-10

申请号：US15381501

申请日：2016-12-16

Applicant: STMicroelectronics International N.V.

Inventor： Harsh Rawat ,  Abhishek Pathak

IPC: G11C11/00 ,  G11C11/419 ,  H01L27/11 ,  G11C11/412

CPC classification number: G11C11/419 ,  G11C7/227 ,  G11C11/412 ,  G11C11/418

Abstract: Disclosed herein is an electronic device including a bit line and a complementary bit line, first and second cross coupled inverters, a first pass gate coupled between the complementary bit line and the first inverter, and a second pass gate coupled between the bit line and the second inverter. The electronic device also includes third and fourth cross coupled inverters, a third pass gate coupled between the complementary bit line and the third inverter, and a fourth pass gate coupled between the bit line and the fourth inverter. The first, second, and fourth inverters are powered between a supply node and a reference node, and the third inverter is powered between a floating node and the reference node. The first pass gate and third pass gate are coupled in parallel.

公开(公告)号：US12046324B2

公开(公告)日：2024-07-23

申请号：US17861458

申请日：2022-07-11

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics (Crolles 2) SAS

Inventor： Harsh Rawat ,  Praveen Kumar Verma ,  Promod Kumar ,  Christophe Lecocq

IPC: G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C8/08 ,  G11C8/10 ,  G11C11/00

CPC classification number: G11C8/10 ,  G11C7/1087 ,  G11C7/222 ,  G11C8/08

Abstract: A memory circuit includes an array of memory cells arranged with first word lines connected to a first sub-array storing less significant bits of data and second word lines connected to a second sub-array storing more significant bits of data. A row decoder circuit coupled to the first and second word lines generates word line signals. A word line gating circuit is configured to selectively gate passage of the word line signals to the second word lines for the second sub-array in response to assertion of a maximum value signal. A data modification circuit performs a mathematical operation on data read from the array of memory cells, and asserts the maximum value signal if the mathematical operation performed on the less significant bits of data from the first sub-array produces a maximum data value.

公开(公告)号：US10032506B2

公开(公告)日：2018-07-24

申请号：US15375987

申请日：2016-12-12

Applicant: STMicroelectronics International N.V.

Inventor： Harsh Rawat ,  Abhishek Pathak

IPC: G11C7/22 ,  G11C7/06 ,  G11C11/419 ,  G11C11/418 ,  G06F1/06 ,  G06F13/16

CPC classification number: G11C11/419 ,  G06F1/06 ,  G06F13/1689 ,  G11C7/1075 ,  G11C8/16 ,  G11C11/413 ,  G11C11/418

Abstract: A memory array has word lines and bit lines. A row decoder is operable to decode a row address and select a corresponding word line. A read-write clock generator is operable to generate a hold clock signal. An address clock generator receives a read address, a write address, a dual port mode control signal, a read chip select signal, and a write chip select signal. When operating in dual port mode, and when operating in a read mode, the address clock generator applies a read delay to the read address and outputs the read address, as delayed, to the row pre-decoder as the address in response to the hold clock signal.

公开(公告)号：US20150212945A1

公开(公告)日：2015-07-30

申请号：US14166003

申请日：2014-01-28

Applicant: STMicroelectronics International N.V.

Inventor： Piyush Jain ,  Harsh Rawat ,  Gangaikondan Subramani Visweswaran

IPC: G06F12/08

CPC classification number: G06F12/0864 ,  G06F2212/6032

Abstract: A cache includes a number of cache ways each having tag memory fields and corresponding data fields. With a simultaneous read-write operation defined by a read memory address (read tag portion and read index portion) and a write memory address (write tag portion and write index portion), the cache determines a read cache hit and reads from one cache way as indicated by the read tag and index portions of the read memory address. Furthermore, a determination is made as to whether a write as indicated by the write tag and index portions of the write memory address would be made in a same one cache way as the read so as to be in conflict. If such a conflict exists, the write is instead effectuated, simultaneously with the read to the one cache way, to a different cache way than is used for the read.

Abstract translation: 缓存包括多个高速缓存路径，每个高速缓存路径具有标签存储器字段和对应的数据字段。 通过由读取存储器地址（读取标签部分和读取索引部分）和写入存储器地址（写入标签部分和写入索引部分）定义的同时读取操作，高速缓存确定读取高速缓存命中并从一种高速缓存读取 如读取的存储器地址的读取标签和索引部分所示。 此外，确定写入存储器地址的写入标签和索引部分所指示的写入是否将以与读取相同的一种高速缓存方式进行，以便被冲突。 如果存在这样的冲突，则写入将与读取到一个缓存方式同时实现到与用于读取的不同的缓存方式。

公开(公告)号：US12183424B2

公开(公告)日：2024-12-31

申请号：US17954060

申请日：2022-09-27

Applicant: STMicroelectronics International N.V.

Inventor： Harsh Rawat ,  Kedar Janardan Dhori ,  Promod Kumar ,  Nitin Chawla ,  Manuj Ayodhyawasi

IPC: G11C7/10 ,  G11C7/12

Abstract: A memory array includes a plurality of bit-cells arranged as a set of rows of bit-cells intersecting a plurality of columns. The memory array also includes a plurality of in-memory-compute (IMC) cells arranged as a set of rows of IMC cells intersecting the plurality of columns of the memory array. Each of the IMC cells of the memory array includes a first bit-cell having a latch, a write-bit line and a complementary write-bit line, and a second bit-cell having a latch, a write-bit line and a complementary write-bit line, wherein the write-bit line of the first bit-cell is coupled to the complementary write-bit line of the second bit-cell and the complementary write-bit line of the first bit-cell is coupled to the write-bit line of the second bit-cell.

公开(公告)号：US12159689B2

公开(公告)日：2024-12-03

申请号：US17853026

申请日：2022-06-29

Applicant: STMicroelectronics International N.V.

Inventor： Praveen Kumar Verma ,  Promod Kumar ,  Harsh Rawat

IPC: G11C8/20 ,  G11C11/418

Abstract: A method of corrupting contents of a memory array includes asserting a signal at a reset node to thereby cause starving of current supply to the memory array, and selecting bit lines and complementary bit lines associated with desired columns of the memory array that contain memory cells to have their contents corrupted. For each desired column, a logic state of its bit line and complementary bit line are forced to a same logic state. Each word line associated with desired rows of the memory array that contains memory cells to have their contents corrupted is simultaneously asserted, and then simultaneously deasserted to thereby place each memory cell to have its contents corrupted into a metastable state during a single clock cycle.