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    Static random access memory supporting a single clock cycle read-modify-write operation
    1.
    发明授权
    Static random access memory supporting a single clock cycle read-modify-write operation 有权

    公开(公告)号：US12040013B2

    公开(公告)日：2024-07-16

    申请号：US17861384

    申请日：2022-07-11

    Applicant: STMicroelectronics International N.V.

    Inventor： Praveen Kumar Verma ,  Harsh Rawat

    IPC: G11C11/419 ,  G11C11/418

    CPC classification number: G11C11/419 ,  G11C11/418

    Abstract: A memory array includes memory cells forming a data word location accessed in response to a word line signal. A data sensing circuit configured to sense data on bit lines associated with the memory cells. The sensed data corresponds to a current data word stored at the data word location. A data latching circuit latches the sensed data for the current data word from the data sensing circuit. A data modification circuit then performs a mathematical modify operation on the current data word to generate a modified data word. The modified data word is then applied by a data writing circuit to the bit lines for writing back to the memory cells of the memory array at the data word location. The operations are advantageously performed within a single clock cycle.

    SRAM with fast, controlled peak current, power efficient array reset, and data corruption modes for secure applications
    3.
    发明授权
    SRAM with fast, controlled peak current, power efficient array reset, and data corruption modes for secure applications 有权

    公开(公告)号：US12159689B2

    公开(公告)日：2024-12-03

    申请号：US17853026

    申请日：2022-06-29

    Applicant: STMicroelectronics International N.V.

    Inventor： Praveen Kumar Verma ,  Promod Kumar ,  Harsh Rawat

    IPC: G11C8/20 ,  G11C11/418

    Abstract: A method of corrupting contents of a memory array includes asserting a signal at a reset node to thereby cause starving of current supply to the memory array, and selecting bit lines and complementary bit lines associated with desired columns of the memory array that contain memory cells to have their contents corrupted. For each desired column, a logic state of its bit line and complementary bit line are forced to a same logic state. Each word line associated with desired rows of the memory array that contains memory cells to have their contents corrupted is simultaneously asserted, and then simultaneously deasserted to thereby place each memory cell to have its contents corrupted into a metastable state during a single clock cycle.

    Low power and fast memory reset
    6.
    发明授权
    Low power and fast memory reset 有权

    公开(公告)号：US12068026B2

    公开(公告)日：2024-08-20

    申请号：US17852677

    申请日：2022-06-29

    Applicant: STMicroelectronics International N.V.

    Inventor： Harsh Rawat ,  Praveen Kumar Verma

    IPC: G11C11/419 ,  G11C11/412

    CPC classification number: G11C11/419 ,  G11C11/412

    Abstract: A method of memory reset includes precharging bit lines of a memory array, asserting a signal at a reset node to remove the precharge voltage, and selecting write drivers associated with the bit lines associated with columns of the memory array that contain memory cells to be reset, with the assertion of the signal at the reset node also resulting in application of desired logic states to inputs of the selected write drivers to cause those selected write drivers to change a logic state of the bit lines associated with those write drivers. The method continues with asserting each word line associated with a row of the memory that contains memory cells to be reset to write desired logic states to all of the memory cells of the columns and rows of the memory to be reset during a single clock cycle, and then deasserting those word lines.

    TEMPERATURE COMPENSATED READ ASSIST CIRCUIT FOR A STATIC RANDOM ACCESS MEMORY (SRAM)
    7.
    发明申请
    TEMPERATURE COMPENSATED READ ASSIST CIRCUIT FOR A STATIC RANDOM ACCESS MEMORY (SRAM) 有权

    公开(公告)号：US20170301396A1

    公开(公告)日：2017-10-19

    申请号：US15132680

    申请日：2016-04-19

    Applicant: STMicroelectronics International N.V.

    Inventor： Kedar Janardan Dhori ,  Ashish Kumar ,  Hitesh Chawla ,  Praveen Kumar Verma

    IPC: G11C11/419

    CPC classification number: G11C11/419 ,  G11C8/08 ,  G11C11/418

    Abstract: A memory circuit includes a wordline, memory cells connected to the wordline and a wordline driver circuit including a p-channel pull-up transistor. The memory circuit further includes a read assist circuit including an n-channel pull-down transistor having a source-drain path connected between the wordline and a ground node and an n-channel diode-connected transistor having a source-drain path connected between a positive supply node and a gate terminal of the n-channel pull-down transistor. The n-channel diode-connected transistor is configured to apply a biasing voltage to the gate terminal of the n-channel pull-down transistor that is a relatively lower voltage for relatively lower temperatures and a relatively higher voltage for relatively higher temperatures.

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