Invention Grant
- Patent Title: Multi-transistor stack architecture in a single vertical stack
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Application No.: US17980345Application Date: 2022-11-03
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Publication No.: US12040232B2Publication Date: 2024-07-16
- Inventor: Amit Chhabra , David Victor Pietromonaco
- Applicant: Arm Limited
- Applicant Address: GB Cambridge
- Assignee: Arm Limited
- Current Assignee: Arm Limited
- Current Assignee Address: GB Cambridge
- Agency: Pramudji Law Group PLLC
- Agent Ari Pramudji
- Main IPC: H01L27/088
- IPC: H01L27/088 ; H01L21/822 ; H01L21/8234 ; H01L21/8238 ; H01L27/092

Abstract:
Various implementations described herein relate to a method for manufacturing, or causing to be manufactured, multiple devices packaged within a single semiconductor die. The multiple devices may have first devices that are arranged in a first multi-transistor stack with a first P-N configuration. The multiple devices may have second devices that are arranged in a second multi-transistor stack with a second P-N configuration that is different than the first P-N configuration.
Public/Granted literature
- US20230118510A1 Multi-Transistor Stack Architecture Public/Granted day:2023-04-20
Information query
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