Invention Grant
- Patent Title: Prevention of contact bottom void in semiconductor fabrication
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Application No.: US17838645Application Date: 2022-06-13
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Publication No.: US12062578B2Publication Date: 2024-08-13
- Inventor: Yun Lee , Chung-Ting Ko , Chen-Ming Lee , Mei-Yun Wang , Fu-Kai Yang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
- Current Assignee Address: TW Hsinchu
- Agency: HAYNES AND BOONE, LLP
- The original application number of the division: US16242720 2019.01.08
- Main IPC: H01L27/01
- IPC: H01L27/01 ; H01L21/285 ; H01L21/768 ; H01L21/8234 ; H01L23/485 ; H01L23/532 ; H01L27/088 ; H01L27/12 ; H01L29/66 ; H01L23/522 ; H01L23/528 ; H01L29/417

Abstract:
A method for semiconductor fabrication includes providing a device structure having an isolation structure, a fin adjacent the isolation structure, gate structures over the fin and the isolation structure, one or more dielectric layers over the isolation structure and the fin and between the gate structures, a first contact hole over the fin, and a second contact hole over the isolation structure. The method further includes depositing a protection layer and treating it with a plasma so that the protection layer in the first contact hole and the protection layer in the second contact hole have different etch selectivity in an etching process; and etching the protection layer to etch through the protection layer on the bottom surface of the first contact hole without etching through the protection layer on the bottom surface of the second contact hole.
Public/Granted literature
- US20220301940A1 Prevention of Contact Bottom Void in Semiconductor Fabrication Public/Granted day:2022-09-22
Information query
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