公开(公告)号：US12119378B2

公开(公告)日：2024-10-15

申请号：US17121073

申请日：2020-12-14

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jia-Heng Wang ,  I-Wen Wu ,  Chen-Ming Lee ,  Fu-Kai Yang ,  Mei-Yun Wang

IPC分类号： H01L29/417 ,  H01L21/02 ,  H01L21/225 ,  H01L21/268 ,  H01L21/311 ,  H01L29/08 ,  H01L29/40 ,  H01L29/78

CPC分类号： H01L29/0847 ,  H01L21/02236 ,  H01L21/2253 ,  H01L21/268 ,  H01L21/31111 ,  H01L21/31116 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/785

摘要： A semiconductor structure includes semiconductor fins disposed over a substrate, an epitaxial source/drain (S/D) feature disposed over the semiconductor fins, where a top surface portion of the epitaxial S/D feature includes two surfaces slanted downward toward each other at an angle, a silicide layer disposed conformally over the top portion of the epitaxial S/D feature, and an S/D contact disposed over the silicide layer, where a bottom portion of the S/D contact extends into the epitaxial S/D feature.

公开(公告)号：US20240297236A1

公开(公告)日：2024-09-05

申请号：US18648069

申请日：2024-04-26

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chun-Han Chen ,  Chen-Ming Lee ,  Fu-Kai Yang ,  Mei-Yun Wang

IPC分类号： H01L29/51 ,  H01L21/02 ,  H01L21/3105 ,  H01L29/40 ,  H01L29/78

CPC分类号： H01L29/511 ,  H01L21/02271 ,  H01L21/31053 ,  H01L29/401 ,  H01L29/7851

摘要： A semiconductor structure includes a fin protruding from a substrate, a first and a second metal gate stacks disposed over the fin, and a dielectric feature defining a sidewall of each of the first and the second metal gate stacks. Furthermore, the dielectric feature includes a two-layer structure, where sidewalls of the first layer are defined by the second layer, and where the first and the second layers have different compositions.

公开(公告)号：US12057488B2

公开(公告)日：2024-08-06

申请号：US17850393

申请日：2022-06-27

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chun-Han Chen ,  Chen-Ming Lee ,  Fu-Kai Yang ,  Mei-Yun Wang

IPC分类号： H01L29/51 ,  H01L21/02 ,  H01L21/3105 ,  H01L29/40 ,  H01L29/78

CPC分类号： H01L29/511 ,  H01L21/02271 ,  H01L21/31053 ,  H01L29/401 ,  H01L29/7851

摘要： A semiconductor structure includes a fin protruding from a substrate, a first and a second metal gate stacks disposed over the fin, and a dielectric feature defining a sidewall of each of the first and the second metal gate stacks. Furthermore, the dielectric feature includes a two-layer structure, where sidewalls of the first layer are defined by the second layer, and where the first and the second layers have different compositions.

公开(公告)号：US20240096999A1

公开(公告)日：2024-03-21

申请号：US18520326

申请日：2023-11-27

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kai-Di Tzeng ,  Chen-Ming Lee ,  Fu-Kai Yang ,  Mei-Yun Wang

IPC分类号： H01L29/45 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/40 ,  H01L29/417 ,  H01L29/78

CPC分类号： H01L29/45 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/785

摘要： A device includes a gate stack; a gate spacer on a sidewall of the gate stack; a source/drain region adjacent the gate stack; a silicide; and a source/drain contact electrically connected to the source/drain region through the silicide. The silicide includes a conformal first portion in the source/drain region, the conformal first portion comprising a metal and silicon; and a conformal second portion over the conformal first portion, the conformal second portion further disposed on a sidewall of the gate spacer, the conformal second portion comprising the metal, silicon, and nitrogen.

公开(公告)号：US11855169B2

公开(公告)日：2023-12-26

申请号：US17826673

申请日：2022-05-27

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kai-Di Tzeng ,  Chen-Ming Lee ,  Fu-Kai Yang ,  Mei-Yun Wang

IPC分类号： H01L29/45 ,  H01L29/78 ,  H01L29/417 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/40

CPC分类号： H01L29/45 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/785

摘要： A device includes a gate stack; a gate spacer on a sidewall of the gate stack; a source/drain region adjacent the gate stack; a silicide; and a source/drain contact electrically connected to the source/drain region through the silicide. The silicide includes a conformal first portion in the source/drain region, the conformal first portion comprising a metal and silicon; and a conformal second portion over the conformal first portion, the conformal second portion further disposed on a sidewall of the gate spacer, the conformal second portion comprising the metal, silicon, and nitrogen.

公开(公告)号：US20220336592A1

公开(公告)日：2022-10-20

申请号：US17854817

申请日：2022-06-30

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ting Fang ,  Chung-Hao Cai ,  Jui-Ping Lin ,  Chia-Hsien Yao ,  Chen-Ming Lee ,  Fu-Kai Yang ,  Mei-Yun Wang

IPC分类号： H01L29/40 ,  H01L21/311 ,  H01L21/321 ,  H01L29/06 ,  H01L29/417 ,  H01L29/78

摘要： A method according to the present disclosure includes receiving a workpiece that includes a gate structure, a first gate spacer feature, a second gate spacer feature, a gate-top dielectric feature over the gate structure, the first gate spacer feature and the second gate spacer feature, a first source/drain feature over a first source/drain region, a second source/drain feature over a second source/drain region, a first dielectric layer over the first source/drain feature, and a second dielectric layer over the second source/drain feature. The method further includes replacing a top portion of the first dielectric layer with a first hard mask layer, forming a second hard mask layer over the first hard mask layer while the second dielectric layer is exposed, etching the second dielectric layer to form a source/drain contact opening and to expose the second source/drain feature, and forming a source/drain contact over the second source/drain feature.

公开(公告)号：US20220301940A1

公开(公告)日：2022-09-22

申请号：US17838645

申请日：2022-06-13

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yun Lee ,  Chung-Ting Ko ,  Chen-Ming Lee ,  Mei-Yun Wang ,  Fu-Kai Yang

IPC分类号： H01L21/8234 ,  H01L27/088 ,  H01L21/768 ,  H01L23/532 ,  H01L21/285 ,  H01L29/66 ,  H01L23/485

摘要： A method for semiconductor fabrication includes providing a device structure having an isolation structure, a fin adjacent the isolation structure, gate structures over the fin and the isolation structure, one or more dielectric layers over the isolation structure and the fin and between the gate structures, a first contact hole over the fin, and a second contact hole over the isolation structure. The method further includes depositing a protection layer and treating it with a plasma so that the protection layer in the first contact hole and the protection layer in the second contact hole have different etch selectivity in an etching process; and etching the protection layer to etch through the protection layer on the bottom surface of the first contact hole without etching through the protection layer on the bottom surface of the second contact hole.

公开(公告)号：US11217492B2

公开(公告)日：2022-01-04

申请号：US16688138

申请日：2019-11-19

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shao-Ming Koh ,  Chen-Ming Lee ,  I-Wen Wu ,  Fu-Kai Yang ,  Jia-Heng Wang ,  Mei-Yun Wang

IPC分类号： H01L21/8238 ,  H01L29/78 ,  H01L27/06 ,  H01L21/02 ,  H01L21/324 ,  H01L21/768 ,  H01L23/535 ,  H01L27/092 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/167 ,  H01L29/45 ,  H01L29/165 ,  H01L29/66 ,  H01L21/306 ,  H01L21/3065

摘要： A method includes providing a structure that includes a substrate, a first gate structure and a second gate structure over the substrate, and a first source/drain (S/D) feature and a second S/D feature over the substrate. The first S/D feature is adjacent to the first gate structure, the second S/D feature is adjacent to the second gate structure, the first S/D feature is configured for an n-type transistor, and the second S/D feature is configured for a p-type transistor. The method further includes introducing a p-type dopant into both the first and the second S/D features. After the introducing of the p-type dopant, the method further includes performing an etching process to the first and the second S/D features, wherein the etching process etches the first S/D feature faster than it etches the second S/D feature.

公开(公告)号：US20210366786A1

公开(公告)日：2021-11-25

申请号：US16881979

申请日：2020-05-22

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chun-Han Chen ,  Chen-Ming Lee ,  Fu-Kai Yang ,  Mei-Yun Wang

IPC分类号： H01L21/8238 ,  H01L29/08 ,  H01L29/165 ,  H01L29/267 ,  H01L29/417 ,  H01L29/45 ,  H01L29/78 ,  H01L21/02 ,  H01L21/311 ,  H01L21/285 ,  H01L29/66 ,  H01L27/092

摘要： In an embodiment, a device includes: a semiconductor substrate; a first fin extending from the semiconductor substrate; a second fin extending from the semiconductor substrate; an epitaxial source/drain region including: a main layer in the first fin and the second fin, the main layer including a first semiconductor material, the main layer having a upper faceted surface and a lower faceted surface, the upper faceted surface and the lower faceted surface each being raised from respective surfaces of the first fin and the second fin; and a semiconductor contact etch stop layer (CESL) contacting the upper faceted surface and the lower faceted surface of the main layer, the semiconductor CESL including a second semiconductor material, the second semiconductor material being different from the first semiconductor material.

公开(公告)号：US20210183696A1

公开(公告)日：2021-06-17

申请号：US17169989

申请日：2021-02-08

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chun-Han Chen ,  I-Wen Wu ,  Chen-Ming Lee ,  Fu-Kai Yang ,  Mei-Yun Wang ,  Chung-Ting Ko ,  Jr-Hung Li ,  Chi On Chui

IPC分类号： H01L21/768 ,  H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L29/40 ,  H01L29/417

摘要： In an embodiment, a method includes: forming a differential contact etch stop layer (CESL) having a first portion over a source/drain region and a second portion along a gate stack, the source/drain region being in a substrate, the gate stack being over the substrate proximate the source/drain region, a first thickness of the first portion being greater than a second thickness of the second portion; depositing a first interlayer dielectric (ILD) over the differential CESL; forming a source/drain contact opening in the first ILD; forming a contact spacer along sidewalls of the source/drain contact opening; after forming the contact spacer, extending the source/drain contact opening through the differential CESL; and forming a first source/drain contact in the extended source/drain contact opening, the first source/drain contact physically and electrically coupling the source/drain region, the contact spacer physically separating the first source/drain contact from the first ILD.