公开(公告)号：US20240389293A1

公开(公告)日：2024-11-21

申请号：US18785442

申请日：2024-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun Po Chang ,  Chen-Ming Lee ,  Fu-Kai Yang ,  Mei-Yun Wang ,  Wei-Yang Lee ,  Tzu-Hsiang Hsu

IPC: H10B10/00 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes a layer having a semiconductive material. The layer includes an outwardly-protruding fin structure. An isolation structure is disposed over the layer but not over the fin structure. A first spacer and a second spacer are each disposed over the isolation structure and on sidewalls of the fin structure. The first spacer is disposed on a first sidewall of the fin structure. The second spacer is disposed on a second sidewall of the fin structure opposite the first sidewall. The second spacer is substantially taller than the first spacer. An epi-layer is grown on the fin structure. The epi-layer protrudes laterally. A lateral protrusion of the epi-layer is asymmetrical with respect to the first side and the second side.

公开(公告)号：US20240379378A1

公开(公告)日：2024-11-14

申请号：US18781018

申请日：2024-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pang-Sheng Chang ,  Yu-Feng Yin ,  Chao-Hsun Wang ,  Kuo-Yi Chao ,  Fu-Kai Yang ,  Mei-Yun Wang ,  Feng-Yu Chang ,  Chen-Yuan Kao ,  Chia-Yang Hung ,  Chia-Sheng Chang ,  Shu-Huei Suen ,  Jyu-Horng Shieh ,  Sheng-Liang Pan ,  Jack Kuo-Ping Kuo ,  Shao-Jyun Wu

IPC: H01L21/321 ,  H01L21/28 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor structure includes a metal gate structure including a gate dielectric layer and a gate electrode, a conductive layer disposed on the gate electrode, and a gate contact disposed on the conductive layer. The conductive layer extends from a position below a top surface of the metal gate structure to a position above the top surface of the metal gate structure. The gate electrode includes at least a first metal, and the conductive layer includes at least the first metal and a second metal different from the first metal. Laterally the conductive layer is fully between opposing sidewalls of the metal gate structure.

公开(公告)号：US20240371938A1

公开(公告)日：2024-11-07

申请号：US18777250

申请日：2024-07-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jia-Heng Wang ,  I-Wen Wu ,  Chen-Ming Lee ,  Fu-Kai Yang ,  Mei-Yun Wang

IPC: H01L29/08 ,  H01L21/02 ,  H01L21/225 ,  H01L21/268 ,  H01L21/311 ,  H01L29/40 ,  H01L29/417 ,  H01L29/78

Abstract: A semiconductor structure includes semiconductor fins disposed over a substrate, an epitaxial source/drain (S/D) feature disposed over the semiconductor fins, where a top surface portion of the epitaxial S/D feature includes two surfaces slanted downward toward each other at an angle, a silicide layer disposed conformally over the top portion of the epitaxial S/D feature, and an S/D contact disposed over the silicide layer, where a bottom portion of the S/D contact extends into the epitaxial S/D feature.

公开(公告)号：US12125879B2

公开(公告)日：2024-10-22

申请号：US18360495

申请日：2023-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： I-Wen Wu ,  Chen-Ming Lee ,  Fu-Kai Yang ,  Mei-Yun Wang ,  Chun-An Lin ,  Wei-Yuan Lu ,  Guan-Ren Wang ,  Peng Wang

IPC: H01L29/08 ,  H01L21/02 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L21/02532 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of semiconductor fabrication includes providing a semiconductor structure having a substrate and first, second, third, and fourth fins above the substrate. The method further includes forming an n-type epitaxial source/drain (S/D) feature on the first and second fins, forming a p-type epitaxial S/D feature on the third and fourth fins, and performing a selective etch process on the semiconductor structure to remove upper portions of the n-type epitaxial S/D feature and the p-type epitaxial S/D feature such that more is removed from the n-type epitaxial S/D feature than the p-type epitaxial S/D feature.

公开(公告)号：US20240347623A1

公开(公告)日：2024-10-17

申请号：US18753240

申请日：2024-06-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Gang Chen ,  Tai-Chun Huang ,  Ming-Chang Wen ,  Shu-Yuan Ku ,  Fu-Kai Yang ,  Tze-Liang Lee ,  Yung-Cheng Lu ,  Yi-Ting Fu

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L21/31116 ,  H01L21/76224 ,  H01L21/76816 ,  H01L21/76897 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/785

Abstract: A method includes forming a first and a second dummy gate stack crossing over a semiconductor region, forming an ILD to embed the first and the second dummy gate stacks therein, replacing the first and the second dummy gate stacks with a first and a second replacement gate stack, respectively, performing a first etching process to form a first opening. A portion of the first replacement gate stack and a portion of the second replacement gate stack are removed. The method further includes filling the first opening to form a dielectric isolation region, performing a second etching process to form a second opening, with the ILD being etched, and the dielectric isolation region being exposed to the second opening, forming a contact spacer in the second opening, and filling a contact plug in the second opening. The contact plug is between opposite portions of the contact spacer.

公开(公告)号：US12062578B2

公开(公告)日：2024-08-13

申请号：US17838645

申请日：2022-06-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun Lee ,  Chung-Ting Ko ,  Chen-Ming Lee ,  Mei-Yun Wang ,  Fu-Kai Yang

IPC: H01L27/01 ,  H01L21/285 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/485 ,  H01L23/532 ,  H01L27/088 ,  H01L27/12 ,  H01L29/66 ,  H01L23/522 ,  H01L23/528 ,  H01L29/417

CPC classification number: H01L21/823475 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/823431 ,  H01L21/823481 ,  H01L23/485 ,  H01L23/53209 ,  H01L27/0886 ,  H01L29/66795 ,  H01L21/76805 ,  H01L21/76855 ,  H01L23/5226 ,  H01L23/5283 ,  H01L29/41791

Abstract: A method for semiconductor fabrication includes providing a device structure having an isolation structure, a fin adjacent the isolation structure, gate structures over the fin and the isolation structure, one or more dielectric layers over the isolation structure and the fin and between the gate structures, a first contact hole over the fin, and a second contact hole over the isolation structure. The method further includes depositing a protection layer and treating it with a plasma so that the protection layer in the first contact hole and the protection layer in the second contact hole have different etch selectivity in an etching process; and etching the protection layer to etch through the protection layer on the bottom surface of the first contact hole without etching through the protection layer on the bottom surface of the second contact hole.

公开(公告)号：US12051735B2

公开(公告)日：2024-07-30

申请号：US17664479

申请日：2022-05-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Gang Chen ,  Tai-Chun Huang ,  Ming-Chang Wen ,  Shu-Yuan Ku ,  Fu-Kai Yang ,  Tze-Liang Lee ,  Yung-Cheng Lu ,  Yi-Ting Fu

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L21/31116 ,  H01L21/76224 ,  H01L21/76816 ,  H01L21/76897 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/785

Abstract: A method includes forming a first and a second dummy gate stack crossing over a semiconductor region, forming an ILD to embed the first and the second dummy gate stacks therein, replacing the first and the second dummy gate stacks with a first and a second replacement gate stack, respectively, performing a first etching process to form a first opening. A portion of the first replacement gate stack and a portion of the second replacement gate stack are removed. The method further includes filling the first opening to form a dielectric isolation region, performing a second etching process to form a second opening, with the ILD being etched, and the dielectric isolation region being exposed to the second opening, forming a contact spacer in the second opening, and filling a contact plug in the second opening. The contact plug is between opposite portions of the contact spacer.

公开(公告)号：US20230402531A1

公开(公告)日：2023-12-14

申请号：US18357307

申请日：2023-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jia-Heng Wang ,  Chun-Han Chen ,  I-Wen Wu ,  Chen-Ming Lee ,  Fu-Kai Yang ,  Mei-Yun Wang

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/3213 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L29/0653 ,  H01L21/32136 ,  H01L21/823431 ,  H01L29/7851

Abstract: The present disclosure provides semiconductor devices and methods of forming the same. A semiconductor device according to one embodiment of the present disclosure includes a first fin-shaped structure extending lengthwise along a first direction over a substrate, a first epitaxial feature over a source/drain region of the first fin-shaped structure, a gate structure disposed over a channel region of the first fin-shaped structure and extending along a second direction perpendicular to the first direction, and a source/drain contact over the first epitaxial feature. The bottom surface of the gate structure is closer to the substrate than a bottom surface of the source/drain contact.

公开(公告)号：US11843028B2

公开(公告)日：2023-12-12

申请号：US17322087

申请日：2021-05-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： I-Wen Wu ,  Fu-Kai Yang ,  Chen-Ming B. Lee ,  Mei-Yun Wang ,  Jr-Hung Li ,  Bo-Cyuan Lu

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/762 ,  H01L21/32

CPC classification number: H01L29/0649 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/0234 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/02274 ,  H01L21/02337 ,  H01L21/02359 ,  H01L21/3105 ,  H01L21/31053 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/7855 ,  H01L21/32 ,  H01L21/823437

Abstract: Semiconductor devices and methods of fabricating semiconductor devices are provided. The present disclosure provides a semiconductor device that includes a first fin structure and a second fin structure each extending from a substrate; a first gate segment over the first fin structure and a second gate segment over the second fin structure; a first isolation feature separating the first and second gate segments; a first source/drain (S/D) feature over the first fin structure and adjacent to the first gate segment; a second S/D feature over the second fin structure and adjacent to the second gate segment; and a second isolation feature also disposed in the trench. The first and second S/D features are separated by the second isolation feature, and a composition of the second isolation feature is different from a composition of the first isolation feature.

公开(公告)号：US20230369223A1

公开(公告)日：2023-11-16

申请号：US18355993

申请日：2023-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Yu Huang ,  Chia-Hsien Yao ,  Fu-Kai Yang ,  Mei-Yun Wang

IPC: H01L23/528 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L23/5286 ,  H01L21/823418 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/66795 ,  H01L29/785

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a dielectric layer formed over a power rail; a bottom semiconductor layer formed over the dielectric layer; a backside spacer formed along a sidewall of the bottom semiconductor layer; a conductive feature contacting a sidewall of the dielectric layer and a sidewall of the backside spacer; channel semiconductor layers over the bottom semiconductor layer, wherein the channel semiconductor layers are stacked up and separated from each other; a metal gate structure wrapping each of the channel semiconductor layers; and an epitaxial source/drain (S/D) feature contacting a sidewall of each of the channel semiconductor layers, wherein the epitaxial S/D feature contacts the conductive feature, and the conductive feature contacts the power rail.