A duty cycle correction device includes a duty cycle correction circuit and a duty cycle control circuit. The duty cycle correction circuit corrects a duty cycle of an input dock signal based on a duty cycle control signal and a duty cycle resolution control signal to generate an output dock signal. The duty cycle control circuit generates the duty cycle control signal by detecting a duty cycle of the output clock signal, generates a duty cycle correction completion signal when duty cycle correction is completed, and recorrects the duty cycle of the input clock signal by activating the duty cycle resolution control signal when the duty cycle correction completion signal is activated at an earlier timing than a reference time.