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    Duty cycle correction device and method
    1.
    发明授权
    Duty cycle correction device and method 有权

    公开(公告)号：US12063042B2

    公开(公告)日：2024-08-13

    申请号：US17945249

    申请日：2022-09-15

    Applicant: SK hynix Inc.

    Inventor： Dae Ho Yang ,  Kwan Su Shon ,  Jong Hun Lim ,  Jun Seo Jang ,  Yo Han Jeong ,  Jaehyeong Hong ,  Byung Joo Hwang

    IPC: H03K5/156 ,  H03K5/135

    CPC classification number: H03K5/1565 ,  H03K5/135

    Abstract: A duty cycle correction device includes a duty cycle correction circuit and a duty cycle control circuit. The duty cycle correction circuit corrects a duty cycle of an input dock signal based on a duty cycle control signal and a duty cycle resolution control signal to generate an output dock signal. The duty cycle control circuit generates the duty cycle control signal by detecting a duty cycle of the output clock signal, generates a duty cycle correction completion signal when duty cycle correction is completed, and recorrects the duty cycle of the input clock signal by activating the duty cycle resolution control signal when the duty cycle correction completion signal is activated at an earlier timing than a reference time.

    DUTY CYCLE CORRECTION DEVICE AND METHOD
    4.
    发明申请
    DUTY CYCLE CORRECTION DEVICE AND METHOD 有权

    公开(公告)号：US20230115436A1

    公开(公告)日：2023-04-13

    申请号：US17945249

    申请日：2022-09-15

    Applicant: SK hynix Inc.

    Inventor： Dae Ho Yang ,  Kwan Su Shon ,  Jong Hun Lim ,  Jun Seo Jang ,  Yo Han Jeong ,  Jae Hyeong Hong ,  Byung Joo Hwang

    IPC: H03K5/156 ,  H03K5/135

    Abstract: A duty cycle correction device includes a duty cycle correction circuit and a duty cycle control circuit. The duty cycle correction circuit corrects a duty cycle of an input clock signal based on a duty cycle control signal and a duty cycle resolution control signal to generate an output clock signal. The duty cycle control circuit generates the duty cycle control signal by detecting a duty cycle of the output clock signal, generates a duty cycle correction completion signal when duty cycle correction is completed, and recorrects the duty cycle of the input clock signal by activating the duty cycle resolution control signal when the duty cycle correction completion signal is activated at an earlier timing than a reference time.

    Impedance calibration circuit and semiconductor memory device including the same
    6.
    发明授权
    Impedance calibration circuit and semiconductor memory device including the same 有权

    公开(公告)号：US10083763B2

    公开(公告)日：2018-09-25

    申请号：US15424547

    申请日：2017-02-03

    Applicant: SK hynix Inc.

    Inventor： Dong Wook Jang ,  Kwan Su Shon ,  Yo Han Jeong

    IPC: G11C29/50 ,  H03K19/00

    CPC classification number: G11C29/50008 ,  G11C29/022 ,  G11C29/028 ,  H03K19/0005

    Abstract: An impedance calibration circuit may be provided. The impedance calibration circuit may include an adjusting circuit. The adjusting circuit may be configured to generate a calibration code based on a variation voltage, which may be applied to a calibration node coupled to a calibration pad, and a reference voltage. The adjusting circuit may be configured to apply a voltage, which may be generated according to a control signal generated based on an operational voltage mode in accordance with the calibration code, to the calibration node. The adjusting circuit may include a plurality of leg circuits. At least one of the leg circuits may include a plurality of legs configured to be selectively coupled to the calibration node based on the control signal.

    Semiconductor memory apparatus, and impedance calibration circuit and method thereof
    7.
    发明授权
    Semiconductor memory apparatus, and impedance calibration circuit and method thereof 有权
    半导体存储装置和阻抗校准电路及其方法

    公开(公告)号：US09478267B1

    公开(公告)日：2016-10-25

    申请号：US14814818

    申请日：2015-07-31

    Applicant: SK hynix Inc.

    Inventor： Yo Han Jeong ,  Kwan Su Shon

    IPC: G11C7/00 ,  G11C7/12

    CPC classification number: G11C29/022 ,  G11C29/028 ,  G11C29/48 ,  G11C29/50008

    Abstract: A semiconductor memory apparatus may include a memory cell array. The semiconductor memory apparatus may include an impedance calibration circuit configured to perform an impedance matching operation by generating an impedance code based on a voltage of an interface node determined by an external reference resistor or an internal reference resistor unit according to whether or not to the external reference resistor is coupled to the impedance calibration circuit. The semiconductor memory apparatus may include a data input/output (I/O) driver configured to receive input data from the memory cell array and generate output data in response to the impedance code.

    Abstract translation: 半导体存储装置可以包括存储单元阵列。 半导体存储装置可以包括：阻抗校准电路，被配置为通过根据外部参考电阻器或内部参考电阻器单元确定的接口节点的电压产生阻抗代码来执行阻抗匹配操作， 参考电阻耦合到阻抗校准电路。 半导体存储装置可以包括数据输入/输出（I / O）驱动器，其被配置为从存储单元阵列接收输入数据并响应于阻抗代码产生输出数据。

    Signal generation apparatus capable of rejecting noise
    8.
    发明授权
    Signal generation apparatus capable of rejecting noise 有权

    公开(公告)号：US12237837B2

    公开(公告)日：2025-02-25

    申请号：US18085333

    申请日：2022-12-20

    Applicant: SK hynix Inc.

    Inventor： Jaehyeong Hong ,  Junseo Jang ,  In Seok Kong ,  Soon Sung An ,  Dae Ho Yang ,  Kwan Su Shon ,  Yo Han Jeong

    IPC: H03K5/1252 ,  G06F1/06 ,  H03K19/21

    Abstract: A signal generation apparatus includes a glitch rejection circuit including n m-stage inverters coupled in series, and configured to receive an input signal and perform an inverting operation on the input signal, based on a plurality of voltage signals, to generate an output signal and adjust switching threshold voltages of the m-stage inverters, based on the plurality of voltage signals, to generate the glitch-removed output signal, when a glitch occurs in the input signal, a level detection circuit to detect a logic level of the output signal provided from the glitch rejection circuit to generate a level detection signal and a complementary level detection signal, and a voltage signal generation circuit configured to receive the input signal, a complementary input signal, the level detection signal, and the complementary level detection signal to generate the plurality of voltage signals and provide the plurality of voltage signals to the glitch rejection circuit.

    Duty cycle detection circuit and duty cycle correction circuit including the same
    10.
    发明授权
    Duty cycle detection circuit and duty cycle correction circuit including the same 有权

    公开(公告)号：US11522529B2

    公开(公告)日：2022-12-06

    申请号：US17229348

    申请日：2021-04-13

    Applicant: SK hynix Inc.

    Inventor： Dae Ho Yang ,  Kwan Su Shon ,  Yo Han Jeong ,  Dong Shin Jo

    IPC: H03K3/017 ,  G11C7/22

    Abstract: Devices and methods for detecting and correcting duty cycles are described. An input switching unit is configured to perform at least one of an operation of outputting differential input signals as a first combination of first and second output signals and an operation of outputting the differential input signals as a second combination of the first and second output signals, according to one of a plurality of control signals. A comparator is configured to receive the first output signal through a first input terminal thereof, to receive the second output signal through a second input terminal thereof, to generate duty detection signals by comparing the signal of the first input terminal and the signal of the second input terminal according to at least another one of the plurality of control signals, and to adjust an offset of at least one of the first input terminal and the second input terminal.

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