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公开(公告)号：US20230115436A1
公开(公告)日：2023-04-13
申请号：US17945249
申请日：2022-09-15
Applicant: SK hynix Inc.
Inventor： Dae Ho Yang , Kwan Su Shon , Jong Hun Lim , Jun Seo Jang , Yo Han Jeong , Jae Hyeong Hong , Byung Joo Hwang
Abstract: A duty cycle correction device includes a duty cycle correction circuit and a duty cycle control circuit. The duty cycle correction circuit corrects a duty cycle of an input clock signal based on a duty cycle control signal and a duty cycle resolution control signal to generate an output clock signal. The duty cycle control circuit generates the duty cycle control signal by detecting a duty cycle of the output clock signal, generates a duty cycle correction completion signal when duty cycle correction is completed, and recorrects the duty cycle of the input clock signal by activating the duty cycle resolution control signal when the duty cycle correction completion signal is activated at an earlier timing than a reference time.
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公开(公告)号：US11983030B1
公开(公告)日：2024-05-14
申请号：US17975890
申请日：2022-10-28
Applicant: SK hynix Inc.
Inventor： Heon Ki Kim , Dae Ho Yang
Abstract: A clock transmission circuit includes a clock driver circuit suitable for transmitting a clock and adjusting a driving force thereof in response to a boosting signal; a low-pass filter circuit suitable for receiving the clock and outputting an initialization signal; and a boosting signal generating circuit suitable for generating the boosting signal that is activated in response to the initialization signal and deactivated in response to the clock.
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公开(公告)号：US11671076B2
公开(公告)日：2023-06-06
申请号：US17979583
申请日：2022-11-02
Applicant: SK hynix Inc.
Inventor： Dae Ho Yang , Kwan Su Shon , Yo Han Jeong , Dong Shin Jo
Abstract: Devices and methods for detecting and correcting duty cycles are described. An input switching unit is configured to perform at least one of an operation of outputting differential input signals as a first combination of first and second output signals and an operation of outputting the differential input signals as a second combination of the first and second output signals, according to one of a plurality of control signals. A comparator is configured to receive the first output signal through a first input terminal thereof, to receive the second output signal through a second input terminal thereof, to generate duty detection signals by comparing the signal of the first input terminal and the signal of the second input terminal according to at least another one of the plurality of control signals, and to adjust an offset of at least one of the first input terminal and the second input terminal.
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公开(公告)号：US12063042B2
公开(公告)日：2024-08-13
申请号：US17945249
申请日：2022-09-15
Applicant: SK hynix Inc.
Inventor： Dae Ho Yang , Kwan Su Shon , Jong Hun Lim , Jun Seo Jang , Yo Han Jeong , Jaehyeong Hong , Byung Joo Hwang
CPC classification number: H03K5/1565 , H03K5/135
Abstract: A duty cycle correction device includes a duty cycle correction circuit and a duty cycle control circuit. The duty cycle correction circuit corrects a duty cycle of an input dock signal based on a duty cycle control signal and a duty cycle resolution control signal to generate an output dock signal. The duty cycle control circuit generates the duty cycle control signal by detecting a duty cycle of the output clock signal, generates a duty cycle correction completion signal when duty cycle correction is completed, and recorrects the duty cycle of the input clock signal by activating the duty cycle resolution control signal when the duty cycle correction completion signal is activated at an earlier timing than a reference time.
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Patent Agency Ranking
公开(公告)号：US20240152174A1
公开(公告)日：2024-05-09
申请号：US17975890
申请日：2022-10-28
Applicant: SK hynix Inc.
Inventor： Heon Ki Kim , Dae Ho Yang
Abstract: A clock transmission circuit includes a clock driver circuit suitable for transmitting a clock and adjusting a driving force thereof in response to a boosting signal; a low-pass filter circuit suitable for receiving the clock and outputting an initialization signal; and a boosting signal generating circuit suitable for generating the boosting signal that is activated in response to the initialization signal and deactivated in response to the clock.
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公开(公告)号：US12237837B2
公开(公告)日：2025-02-25
申请号：US18085333
申请日：2022-12-20
Applicant: SK hynix Inc.
Inventor： Jaehyeong Hong , Junseo Jang , In Seok Kong , Soon Sung An , Dae Ho Yang , Kwan Su Shon , Yo Han Jeong
IPC: H03K5/1252 , G06F1/06 , H03K19/21
Abstract: A signal generation apparatus includes a glitch rejection circuit including n m-stage inverters coupled in series, and configured to receive an input signal and perform an inverting operation on the input signal, based on a plurality of voltage signals, to generate an output signal and adjust switching threshold voltages of the m-stage inverters, based on the plurality of voltage signals, to generate the glitch-removed output signal, when a glitch occurs in the input signal, a level detection circuit to detect a logic level of the output signal provided from the glitch rejection circuit to generate a level detection signal and a complementary level detection signal, and a voltage signal generation circuit configured to receive the input signal, a complementary input signal, the level detection signal, and the complementary level detection signal to generate the plurality of voltage signals and provide the plurality of voltage signals to the glitch rejection circuit.
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公开(公告)号：US11996844B2
公开(公告)日：2024-05-28
申请号：US18106915
申请日：2023-02-07
Applicant: SK hynix Inc.
Inventor： Dae Ho Yang , Min Su Kim , Kwan Su Shon , Keun Seon Ahn , Soon Sung An , Su Han Lee , Jae Hoon Jung , Kyeong Min Chae , Jae Hyeong Hong , Jun Sun Hwang
CPC classification number: H03K3/017 , H03K5/05 , H03K5/135 , H03K5/1565
Abstract: A duty cycle correction circuit includes a duty correction circuit, an information generation circuit and a duty control circuit. The duty correction circuit corrects a duty rate of an input clock signal based on a duty control code to generate an output clock signal. The information generation circuit compares a difference between operation power voltages based on an operation mode to generate voltage information. The duty control circuit receives the voltage information from the information generation circuit and generates the duty control code that includes the voltage information based on a duty rate of the output clock signal.
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公开(公告)号：US11522529B2
公开(公告)日：2022-12-06
申请号：US17229348
申请日：2021-04-13
Applicant: SK hynix Inc.
Inventor： Dae Ho Yang , Kwan Su Shon , Yo Han Jeong , Dong Shin Jo
Abstract: Devices and methods for detecting and correcting duty cycles are described. An input switching unit is configured to perform at least one of an operation of outputting differential input signals as a first combination of first and second output signals and an operation of outputting the differential input signals as a second combination of the first and second output signals, according to one of a plurality of control signals. A comparator is configured to receive the first output signal through a first input terminal thereof, to receive the second output signal through a second input terminal thereof, to generate duty detection signals by comparing the signal of the first input terminal and the signal of the second input terminal according to at least another one of the plurality of control signals, and to adjust an offset of at least one of the first input terminal and the second input terminal.
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公开(公告)号：US11450366B2
公开(公告)日：2022-09-20
申请号：US17331918
申请日：2021-05-27
Applicant: SK hynix Inc.
Inventor： Jin Ha Hwang , Kwang Soon Kim , Dae Ho Yang , Yo Han Jeong , Jun Sun Hwang
Abstract: A dividing circuit system includes a first dividing circuit and a second dividing circuit. The first dividing circuit performs a reset operation based on a reset control signal and generates second and fourth divided clock signals. The second dividing circuit performs a reset operation based on the reset control signal and generates first and third divided clock signals.
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