An electronic device includes a pixel array that outputs a raw image including color pixels and specific pixels, a logic circuit that outputs a first binned image by performing first binning on pixels in a row direction for each unit kernel of the raw image, and a processor that outputs a second binned image by performing second binning on the first binned image. When a unit kernel includes at least one of the specific pixels, a column to which the at least one specific pixel belongs is read out at a readout timing different from a readout timing of a column to which none of the specific pixels belong and undergoes the first binning. The second binning combines a third binned image of the column to which none of the specific pixels belong with a fourth binned image of the column to which the at least one specific pixel belongs.