Invention Grant
- Patent Title: Reduced-power implementation of error-correction processing
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Application No.: US18158720Application Date: 2023-01-24
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Publication No.: US12074612B2Publication Date: 2024-08-27
- Inventor: Daniele Cucchi , Davide Cattaneo , Luca Gabriele Razzetti , Carlo Constantini , Giancarlo Gavioli
- Applicant: Nokia Solutions and Networks Oy
- Applicant Address: FI Espoo
- Assignee: Nokia Solutions and Networks Oy
- Current Assignee: Nokia Solutions and Networks Oy
- Current Assignee Address: FI Espoo
- Agency: Stratford Group Ltd.
- Priority: EP 153102 2022.01.25
- Main IPC: H03M13/11
- IPC: H03M13/11 ; H03M13/00 ; H03M13/37

Abstract:
A low-density parity-check (LDPC) decoder comprising a pre-processor, a core decoder, and a post-processor. The pre-processor is configured to transform a received log-likelihood-ratio (LLR) sequence into a form that enables the core decoder to toggle at a reduced rate during iterative decoding processing thereof. Upon stoppage of the decoding processing corresponding to the LLR sequence, the post-processor operates to apply a complementary transformation to the output of the core decoder, which recovers the corresponding codeword of the LDPC code. An example embodiment of the LDPC decoder operating in this manner may be able to beneficially reduce the power consumption therein by about 10%.
Public/Granted literature
- US20230238983A1 REDUCED-POWER IMPLEMENTATION OF ERROR-CORRECTION PROCESSING Public/Granted day:2023-07-27
Information query
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