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公开(公告)号:US12074612B2
公开(公告)日:2024-08-27
申请号:US18158720
申请日:2023-01-24
Applicant: Nokia Solutions and Networks Oy
Inventor: Daniele Cucchi , Davide Cattaneo , Luca Gabriele Razzetti , Carlo Constantini , Giancarlo Gavioli
CPC classification number: H03M13/1125 , H03M13/1108 , H03M13/1111 , H03M13/3723 , H03M13/6502
Abstract: A low-density parity-check (LDPC) decoder comprising a pre-processor, a core decoder, and a post-processor. The pre-processor is configured to transform a received log-likelihood-ratio (LLR) sequence into a form that enables the core decoder to toggle at a reduced rate during iterative decoding processing thereof. Upon stoppage of the decoding processing corresponding to the LLR sequence, the post-processor operates to apply a complementary transformation to the output of the core decoder, which recovers the corresponding codeword of the LDPC code. An example embodiment of the LDPC decoder operating in this manner may be able to beneficially reduce the power consumption therein by about 10%.
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公开(公告)号:US20230238983A1
公开(公告)日:2023-07-27
申请号:US18158720
申请日:2023-01-24
Applicant: Nokia Solutions and Networks Oy
Inventor: Daniele Cucchi , Davide Cattaneo , Luca Gabriele Razzetti , Carlo Constantini , Giancarlo Gavioli
IPC: H03M13/11
CPC classification number: H03M13/1125 , H03M13/1108
Abstract: A low-density parity-check (LDPC) decoder comprising a pre-processor, a core decoder, and a post-processor. The pre-processor is configured to transform a received log-likelihood-ratio (LLR) sequence into a form that enables the core decoder to toggle at a reduced rate during iterative decoding processing thereof. Upon stoppage of the decoding processing corresponding to the LLR sequence, the post-processor operates to apply a complementary transformation to the output of the core decoder, which recovers the corresponding codeword of the LDPC code. An example embodiment of the LDPC decoder operating in this manner may be able to beneficially reduce the power consumption therein by about 10%.
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