公开(公告)号：US20230403029A1

公开(公告)日：2023-12-14

申请号：US18206161

申请日：2023-06-06

Applicant: Nokia Solutions and Networks Oy

Inventor： Marco Ferrari ,  Alberto Tarable ,  Luca Barletta ,  Giancarlo Gavioli ,  Luca Gabriele Razzetti ,  Carlo Costantini ,  Sara Caobianco ,  Daniele Cucchi ,  Davide Cattaneo

IPC: H03M13/11

CPC classification number: H03M13/1105 ,  H03M13/1151

Abstract: A method and apparatus are provided for decoding a plurality of codewords from a received binary bitstream. A first decoding stage processes each of the codewords with a first iterative decoding algorithm based on forward error-correction information of the codewords. A second decoding stage processes selected ones of the codewords with a second iterative decoding algorithm, which is based on forward error-correction information in the selected ones of the codewords. Each codeword selected for the second decoding stage is selected in response to an exit from the decoding of that codeword without the production of a decoded codeword. The second iterative decoding algorithm is configured to enable a greater number of iterations of decoding per codeword than the first iterative decoding algorithm.

公开(公告)号：US12074612B2

公开(公告)日：2024-08-27

申请号：US18158720

申请日：2023-01-24

Applicant: Nokia Solutions and Networks Oy

Inventor： Daniele Cucchi ,  Davide Cattaneo ,  Luca Gabriele Razzetti ,  Carlo Constantini ,  Giancarlo Gavioli

IPC: H03M13/11 ,  H03M13/00 ,  H03M13/37

CPC classification number: H03M13/1125 ,  H03M13/1108 ,  H03M13/1111 ,  H03M13/3723 ,  H03M13/6502

Abstract: A low-density parity-check (LDPC) decoder comprising a pre-processor, a core decoder, and a post-processor. The pre-processor is configured to transform a received log-likelihood-ratio (LLR) sequence into a form that enables the core decoder to toggle at a reduced rate during iterative decoding processing thereof. Upon stoppage of the decoding processing corresponding to the LLR sequence, the post-processor operates to apply a complementary transformation to the output of the core decoder, which recovers the corresponding codeword of the LDPC code. An example embodiment of the LDPC decoder operating in this manner may be able to beneficially reduce the power consumption therein by about 10%.

公开(公告)号：US20230238983A1

公开(公告)日：2023-07-27

申请号：US18158720

申请日：2023-01-24

Applicant: Nokia Solutions and Networks Oy

Inventor： Daniele Cucchi ,  Davide Cattaneo ,  Luca Gabriele Razzetti ,  Carlo Constantini ,  Giancarlo Gavioli

IPC: H03M13/11

CPC classification number: H03M13/1125 ,  H03M13/1108

Abstract: A low-density parity-check (LDPC) decoder comprising a pre-processor, a core decoder, and a post-processor. The pre-processor is configured to transform a received log-likelihood-ratio (LLR) sequence into a form that enables the core decoder to toggle at a reduced rate during iterative decoding processing thereof. Upon stoppage of the decoding processing corresponding to the LLR sequence, the post-processor operates to apply a complementary transformation to the output of the core decoder, which recovers the corresponding codeword of the LDPC code. An example embodiment of the LDPC decoder operating in this manner may be able to beneficially reduce the power consumption therein by about 10%.