Invention Grant
- Patent Title: Caching lookup tables for block family error avoidance
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Application No.: US17931937Application Date: 2022-09-14
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Publication No.: US12079065B2Publication Date: 2024-09-03
- Inventor: Shakeel Isamohiuddin Bukhari , Mark Ish
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Harrity & Harrity, LLP
- Main IPC: G06F11/00
- IPC: G06F11/00 ; G06F12/02 ; G06F12/12

Abstract:
In some implementations, a memory device may cache a subset of one or more block family error avoidance (BFEA) lookup tables associated with a block family associated with host data in a first memory location. The block family may be based on at least one of a time window during which the host data was written or a temperature window at which the host data was written. The memory device may receive a read command associated with host data and determine, based on the block family and the subset of the one or more BFEA tables, a threshold voltage offset associated with the host data. The memory device may compute a modified threshold voltage by applying the threshold voltage offset to a base read level voltage associated with the host data. The memory device may read, using the modified threshold voltage, the host data from the first memory location.
Public/Granted literature
- US20240069997A1 CACHING LOOKUP TABLES FOR BLOCK FAMILY ERROR AVOIDANCE Public/Granted day:2024-02-29
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