Invention Grant
- Patent Title: Generating integrated circuit floorplans using neural networks
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Application No.: US18310427Application Date: 2023-05-01
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Publication No.: US12086516B2Publication Date: 2024-09-10
- Inventor: Chian-min Richard Ho , William Hang , Mustafa Nazim Yazgan , Anna Darling Goldie , Jeffrey Adgate Dean , Azalia Mirhoseini , Emre Tuncer , Ya Wang , Anand Babu
- Applicant: Google LLC
- Applicant Address: US CA Mountain View
- Assignee: Google LLC
- Current Assignee: Google LLC
- Current Assignee Address: US CA Mountain View
- Agency: Fish & Richardson P.C.
- Main IPC: G06F30/27
- IPC: G06F30/27 ; G06F30/392

Abstract:
Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a computer chip floorplan. One of the methods includes obtaining netlist data for a computer chip; and generating a computer chip floorplan, comprising placing a respective node at each time step in a sequence comprising a plurality of time steps, the placing comprising, for each time step: generating an input representation for the time step; processing the input representation using a node placement neural network having a plurality of network parameters, wherein the node placement neural network is configured to process the input representation in accordance with current values of the network parameters to generate a score distribution over a plurality of positions on the surface of the computer chip; and assigning the node to be placed at the time step to a position from the plurality of positions using the score distribution.
Public/Granted literature
- US20230394203A1 GENERATING INTEGRATED CIRCUIT FLOORPLANS USING NEURAL NETWORKS Public/Granted day:2023-12-07
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