Invention Grant
- Patent Title: Confined epitaxial regions for semiconductor devices
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Application No.: US18120920Application Date: 2023-03-13
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Publication No.: US12094955B2Publication Date: 2024-09-17
- Inventor: Szuya S. Liao , Michael L. Hattendorf , Tahir Ghani
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt P.C.
- The original application number of the division: US15867210 2018.01.10
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L21/8234 ; H01L29/08 ; H01L29/165 ; H01L29/78

Abstract:
Confined epitaxial regions for semiconductor devices and methods of fabricating semiconductor devices having confined epitaxial regions are described. For example, a semiconductor structure includes a plurality of parallel semiconductor fins disposed above and continuous with a semiconductor substrate. An isolation structure is disposed above the semiconductor substrate and adjacent to lower portions of each of the plurality of parallel semiconductor fins. An upper portion of each of the plurality of parallel semiconductor fins protrudes above an uppermost surface of the isolation structure. Epitaxial source and drain regions are disposed in each of the plurality of parallel semiconductor fins adjacent to a channel region in the upper portion of the semiconductor fin. The epitaxial source and drain regions do not extend laterally over the isolation structure. The semiconductor structure also includes one or more gate electrodes, each gate electrode disposed over the channel region of one or more of the plurality of parallel semiconductor fins.
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